Attendees of past Design Automation Conferences (DACs) could count on hearing from EDA vendors and design technologists. This year’s 46th DAC takes a significant step by adding the voices of the tool users themselves. With more than 80 papers focused on the latest in tool use and methodologies, the User Track joins DAC’s technical program when the conference kicks off July 26-31 at the Moscone Center in San Francisco.
The 46th DAC’s technical program comprises a smorgasbord of 54 research paper sessions, featuring 156 talks selected from 733 submissions from around the globe. In the User Track, attendees can hear presentations on a variety of topics such as robust design and test, practical physical design, real-world timing analysis, and front-end power planning and analysis, to name just a few.
A highlight of the conference is sure to come at Monday’s Keynote Panel, in which the CEOs of EDA’s Big Three will chew over their respective visions for the EDA industry’s future. Aart de Geus (Synopsys), Wally Rhines (Mentor Graphics), and Lip- Bu-Tan (Cadence) will take the dais to expound on business and technology issues and to share their respective overall outlooks for EDA. Rhines will return on Thursday to chair a lunch-hour panel session on what “green” means to design automation.
As usual, the DAC program is loaded with opportunities for attendees to learn. The 54 paper sessions are arranged in six parallel tracks that sweep the spectrum of leading-edge EDA technologies. Special session topics include how to prepare for design at 22 nm, designing circuits in the face of uncertainty, verification of large SoCs, bug-tracking in complex designs, and multicore computing.
The 46th DAC program also features panels focused on the hottest issues of the industry, including technical discussions on system prototyping, embedded software design, mixed-signal verification, system-level power challenges, design for manufacturability, and emerging applications of EDA technology.
Finally, six full-day tutorials will be given on Monday and Friday, covering multicore, low-power system-on-a-chip (SoC) design, post-silicon validation and runtime verification, functional verification planning and management, and the challenges of IC design with nanomaterials.
WHAT'S NEW AT THE SYSTEM LEVEL?
High-level synthesis (HLS) continues to be a topic of interest at DAC. Synfora will demo its PICO Extreme Power, a variant of its algorithmic synthesis platform that’s intended to reduce power consumption in mobile devices. PICO Extreme Power is being touted by Synfora as the industry’s first algorithmic synthesis tool to automatically minimize power consumption at the system level based on a variety of techniques, including automatic insertion of multi-level clock gating.
Multi-level clock gating enables clock gating to be applied to a computation block in an application accelerator at any level in the hierarchy. PICO Extreme Power has delivered savings of up to 50% using this technique, a claim backed by results obtained by researchers at Rice University and the Indian Institute of Science.
PICO Extreme Power plays well with Atrenta’s SpyGlass-Power, a tool that delivers accurate RTL power estimates. Designs completed using the two tools in concert showed power reductions of 16% and 53% compared with designs without block-level clock gating.
Speaking of Atrenta, it will continue to expand and refine its focus on early design closure at DAC this year. Whereas conventional flows capture designs at the RTL stage with debug and closure occuring during back-end implementation, Atrenta’s tool suite enables capture of the design at the architectural phase with design closure at RTL.
At DAC, Atrenta will unveil a fully integrated tool suite that allows capture of a design at the specification, or request for quote (RFQ), phase and supports iterative refinement throughout RTL development, resulting in a smooth and predictable handoff to the back-end implementation flow (Fig. 1).
Another HLS stalwart, Forte Design Systems, will display the latest version of its Cynthesizer SystemC HLS software. Cynthesizer 3.6 boasts several new technologies, including SystemC 2.2 support, features for partitioning complex hierarchical systems, control-based design support, memory-handling upgrades, and scalability improvements.
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