Electronic Design

  
Reprints     Printer-Friendly    Email this Article    RSS        Font Size     What's This?


[Leapfrog: First Look]
Mini Ethernet Chip Contends In Low-End Networking Space
With SPI, an Ethernet controller easily interfaces to 8-bit microcontrollers.

William Wong  |   ED Online ID #10118  |   April 28, 2005


Connectivity keeps moving down the food chain. TCP/IP stacks for 8- and 16-bit MCUs are readily available. Yet interfacing an Ethernet controller to one of these compact MCUs has been an exercise in creativity.

Most Ethernet controllers use a parallel interface, such as PCI. Now, thanks to Microchip's latest innovation, an MCU needs only four lines to interface to Ethernet. This was accomplished with a high-speed serial-peripheral-interface (SPI) protocol, which is supported by most 8- and 16-bit MCUs.

The 10BaseT ENC28J60 Ethernet controller comes in a variety of small, 28-pin packages. The four-wire SPI operates at speeds of up to 10 Mbits/s. Contained within the chip are the Ethernet physical-layer device (PHY) and media access controller (MAC), creating a single-chip solution. Thus, even 16-pin MCUs can have Ethernet connectivity, leaving 10 pins for other chores. Microchip has a free TCP/IP stack designed for its PIC18 8-bit MCUs.

The on-chip, 8-kbyte, dual-port SRAM buffers Ethernet packets, and it can be used for off-chip MCU memory. Then, an application can examine, modify, or create new messages using the Ethernet controller's memory. This is crucial for RAM-limited 8- and 16-bit MCUs with lots of flash.

The controller also handles many protocol stack chores. Its programmable filtering can automatically evaluate, accept, or reject Magic Packet, Unicast, Multicast, or broadcast packet types. This is particularly important for minimizing the flash-memory space in the host MCU.

ON-CHIP VERSUS OFF-CHIP
The ENC28J60 has no competition in the 8-bit arena so far, but the 16-bit arena is another matter. A number of 16-bit MCUs with integrated Ethernet PHY and MAC is available.

Freescale's MC9S12NE64 combines a 16-bit HCS12 processor core with an Ethernet MAC and PHY (see EiED Online, "Building A One-Chip Web Server," ED Online 9115). It can use a parallel interface between the microprocessor and the Ethernet controller, because an on-chip interconnect won't affect the number of peripheral pins. On the other hand, the NE64 is a larger chip. Replete with built-in peripherals, it's most appropriate for new designs where its peripheral complement can be considered.

The other downside to a built-in solution is the choice of processors and peripherals. The 8- and 16-bit MCUs are option-prolific. Clearly, combining Ethernet with all of these options is impractical. Microchip's solution allows the addition of Ethernet to almost any design. SPIs are common because other off-chip peripherals employ the same interface.

Some designers say 10BaseT is no longer the standard. This is really a non-issue. Automatic speed negotiation is standard with Ethernet hubs and switches. It's required due to the plethora of devices with different capabilities, from 10BaseT to Gigabit Ethernet.

Another issue involves MCU performance. An 8-bit MCU will have a tough time just keeping up with the throughput of a 10BaseT connection. Luckily, a remote device like this typically will support a single connection to a remote monitoring application.

The ENC28J60 represents a major step forward in low-end networking. Now, CAN (controller-area network) isn't the only economical solution for 8- and 16-bit networking. The ENC28J60 costs $4.17.

Microchip
www.microchip.com

See Associated Figure

ENC28J60 ETHERNET CONTROLLER
Performance: on-chip, 10-Mbit/s Ethernet PHY and MAC

Host interface: 10-Mbit/s SPI

Power requirements: under 140 mA

Footprint: 28-pin SPDIP, SOIC, SSOP, and QFN

Memory: 8-kbyte, dual-port SRAM

Price: $4.17


Reprints   Printer-Friendly  Email this Article  RSS    Font Size   What's This?


  • Network-On-Chip Tools Arrive for The Masses
  • Tackling System Design Challenges Through Early Verification
  • ESL Tools Take Center Stage As Designers Move Up
  • Parasitic Extraction Tool Targets Next-Generation Custom ICs
  • Synopsys Jumps Into ESL-Synthesis Pool
  • Verify Control Systems Before Committing To Hardware
  • You're Using How Many FPGAs?
  • Tool Up For The FPGA Blitz
    1) Build A Smart Battery Charger Using A Single-Transistor Circuit
    (181 views today)
    2) Hot Hands For Some Cool Rock: Motion Sensing Meets Audio Engineering
    (167 views today)
    3) Science Fiction Meets Science Fact In Today's Robot Research
    (99 views today)
    4) GPS-Derived Grandmaster Clock Delivers Ultra-Precise Time And Frequency Sync
    (87 views today)
    5) What's All This Transimpedance Amplifier Stuff, Anyhow? (Part 1)
    (85 views today)
    ALL TOP 20



    POST YOUR COMMENTS HERE
    Name:

    Email:
    Your Comments:

    Enter the text from the image below


    Please refresh the page if you have trouble reading this text.

    Search Electronic Design
         
      
     
    Web Seminar
    Sponsored By:
    Title: Read Pacing: A Performance Enhancing Feature of PCI Express Gen 2 Switch Devices
    Speakers: 
    Date: 07/01/08
    Register: 

    Electronic Design Europe Electronic Design China EEPN Power Electronics Auto Electronics Microwaves & RF
    Mobile Dev & Design Schematics Find Power Products Military Electronics EE Events Related Resources