Figure 1 shows a benign means of interfacing a low-level, wideband differential signal to an analog-to-digital converter (ADC). The FET input stage (AD8066) draws only 6 pA of input bias current and presents only 2 pF of differential input capacitance. The overall circuit has an input referred noise of 10 nV/√Hz and a gain-bandwidth product (GBP) of 2 GHz. It maintains a common-mode rejection ratio (CMRR) of over 90 dB up to 1 MHz, far exceeding the rejection bandwidth of traditional instrumentation amplifiers.
The circuit architecture mimics the standard three-op-amp instrumentation amplifier but employs the AD8129 wideband differential receiver as the difference amplifier stage. The differential input stage, implemented with the AD8066 dual wideband FET-input op amp, is configured for a gain of 5. The AD8129 is configured for a gain of 20, resulting in an overall circuit gain of 100. The excellent common-mode rejection is owed to the AD8129's active common-mode feedback, shown in Figure 2. This results in common-mode rejection superior to that of discrete difference amplifiers built around traditional op amps.
Also shown in the schematic is an optional auto-calibration circuit composed of U3, U4, and U5. When the CAL signal is strobed low, the circuit will drive the common mode of the instrumentation-amp output to the same level as the voltage applied to the VREF input. Typically, the VREF input would be tied to the reference input of a pseudodifferential ADC.
The three main components of the calibration circuit are the AD8605 precision low-voltage op amp (which has been configured as a comparator), an AD5220 digital potentiometer, and an OP1177 buffer amplifier. The comparator determines the polarity of the output offset. This feeds the up/down input of the digital potentiometer, which produces a voltage on its wiper terminal that moves in a direction opposite to the offset. Then, this voltage is buffered and drives the reference input of the instrumentation amp.
The digital potentiometer has 512 positions and covers a span of ±200 mV, so the output offset will be trimmed to within 2 mV. Without the trim, the output offset could be up to ±160 mV, which would consume nearly 2 dB of the dynamic range of an ADC with a 2-V input span.
For best performance, the RC time constants created by R6 × C1 and R8 × C2 should be made roughly equal. The period of the clock feeding the auto-calibration circuit should be at least three times this time constant. Otherwise, the potentiometer will tend to overshoot the optimal value while the comparator input is settling. In this case, the RC time constant is about 5 µs, so the clock period should be greater than about 15 µs.
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