[Product Innovation]
Optimized Synchronous Rectification Drives Up DC-DC Efficiency
A dedicated controller and optimized MOSFETs will boost the efficiency of a synchronous converter to over 90%.
The desire to squeeze more data bits through smaller systems at faster rates has brought about a dramatic rise in power consumption. At the same time, there's been a proliferation of voltages that address the needs of microprocessors, memories, I/Os, and other functions in modern computers and communications equipment. With multimode configurations being the current the trend, power supplies must respond instantly to changing load requirements. The result is the rapid adoption of distributed power architectures, with dc-dc converters in close proximity to the load. These improvements are imposing new challenges in cost and efficiency, as well as power density, on dc-dc converters.
In response, manufacturers continue to miniaturize the converter size while boosting the supply's power density. Users are demanding higher and higher power-conversion efficiencies from tinier and tinier packages, even as output voltages drop below 3.3 V. In the mean time, output voltages drop to 2.0 V and below while output currents surge to tens of amperes, and the input voltage remains as high as 48 V. This makes those manufacturer's tasks even more arduous.
Power-supply designers are responding to these problems by slowly migrating to synchronous-rectification techniques. Of course, low-loss, MOSFET-based synchronous rectification has helped beat the limitations of conventional rectifiers employing Schottky diodes. Those dc-dc converters thereby achieved further improvements in efficiency. There's still ample room for improvement over the current approaches that are self-driven, employ some form of discrete control, and use paralleled MOSFETs for higher output currents.
The self-driven design brings its own set of problems, while the MOSFETs implemented are inappropriate for the application. Specifically, for higher output currents, paralleling power MOSFETs has resulted in an increased footprint, as well as higher I2R losses to degrade the performance of the synchronous rectifier. Higher input voltages and lower output voltages have brought about very low duty cycles, increasing switching losses and decreasing conversion efficiency. In fact, the ratio of VOUT to VIN dictates the duty cycle and, therefore, the timing of the MOSFETs. With lower duty cycles, the MOSFETs must transition or switch faster, so they end up with higher switching losses. Though more prevalent in synchronous buck, this phenomenon is less severe in isolated versions.
So the pressure to improve efficiency without hiking the solution's price tag is enormous. At power outputs of 100 W and above, every percent increase in conversion efficiency makes a difference. Present-day solutions afford nearly 85% efficiency, which is considered high for designs that step down voltages from 48 V to 3.3 V and below.
Boosting that efficiency number to 90% and over for high-power dc-dc converters isn't easy. That reality really puts the spotlight on International Rectifier Corp.'s claims of a ready-made solution. The company has generated a dedicated synchronous-rectification solution that promises to further augment the conversion efficiency by 4% to 5%, thereby pushing that bar above 90%.
To beat out problems with present methods and accomplish more in power-conversion efficiencies, the company has developed an optimized gate-drive scheme. Using stripe-planar process technology, IR specifically crafted low on-resistance HEXFET power MOSFETs that provide the best combination of on-resistance, gate charge, and die size for this application. According to the company, these elements make this a dedicated solution for synchronous rectification.
The current optimized solution is actually tailored for isolated systems employing single-ended forward-converter topology. But IR intends to extend the concept to other topologies like buck, boost, and multiphase, including multi-output configurations. The advantage of the isolated-converter topology is that it employs the transformer's turns ratio to balance the converter duty cycle. That ratio minimizes the switching losses when VOUT drops significantly lower than VIN.
The company states that the dedicated, high-speed CMOS controller chip, IR1175, implements a gate-drive technique to significantly lower losses in isolated topologies implementing synchronous rectification (Fig. 1). To alleviate some of the drawbacks of earlier schemes, the controller IC incorporates several key features. It can compensate for finite MOSFET switching times, so they switch on with the actual transition of the transformer instead of having to do it later. This is accomplished by using a modified phased-locked loop (PLL) with delay block to pre-fire the n-channel MOSFETs.
By providing necessary dead times/overlap between gate drives, the IC also minimizes the effect of stray inductance. It maintains a steady gate drive throughout both power-transfer and reset cycles, regardless of transformer output status. Those gate drives are compatible with logic-level power MOSFETs, independent of transformer output levels.
Finally, the controller follows the transitions of the transformer and maintains the duty-cycle requirements set by the system's pulse-width-modulated controller. Turning the po-wer MOSFETs on or off before the transfor-mer's transitions minimizes body-drain conduction and cuts associated losses, according to Edgar Abdoulin, power systems design engineer.
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