The semiconductor industry’s rapid move toward a 90-nm process node to achieve performance and cost benefits puts enormous pressure on power budgets. Decreasing transistor sizes lead to increased leakage current and, as a result, static power. Dynamic power also rises with system speeds and higher design density, but in a more linear fashion. Today, many designs have 50-50 static and dynamic power dissipation. According to International Technology Roadmap for Semiconductors (ITRS) projections, static power is increasing exponentially at every process node, making innovative process technologies imperative.
With the adoption of FPGAs in more markets and systems every year (driven by increasing performance/density and decreasing price), FPGA power consumption within the entire system is critical. Leading FPGA vendors are already adopting new techniques to mitigate static and dynamic power consumption.
Power-Consumption Considerations
FPGAs and ASICs often make up most of the power being consumed in systems. The focus of this article is on FPGAs, but some of the issues and descriptions of power optimization apply to ASICs as well.
A given system or individual components typically have a power budget, which usually falls into two major areas. The first area is a simple, practical one—choosing the power capacity of the supplies being used in a design to meet the system power needs. The second area is about thermal concerns, which need to be understood to keep the system working within the temperature specifications of the various components. To this end, it’s important to know where power consumption comes from in the FPGAs being chosen, and how one can optimize it.
Working Within A Power Budget
Here’s a typical example of a power budget: A board has a power budget of 20 W, with a normal operating environment of 10° to 40°C. Under conditions of a failed fan(s), ambient air above certain components may rise above 70°C. Many component manufacturers have operating conditions that range up to 85°C junction temperature for commercial grade, and 100°C for industrial-grade parts.
Table 1 shows a set of needs that span component environment, such as temperature, power-supply tolerances, etc. Importantly, it also shows the estimated power consumption (from tools and manufacturers’ datasheets) of each FPGA in the design as well as the ASIC and DDR memory.
The goal is to see if the 20-W power budget can be met. Parts like ASICs, DRAM, etc., come from the manufacturers with fixed maximum power consumption. The remaining components on the board or system are the FPGAs. Using power-estimation tools, we can see where we fall and if we need to optimize our FPGAs’ power consumption. Table 2 shows the various resources being used by the designer inside each FPGA.
For FPGAs, Xilinx tools are available to allow for power prediction (Fig. 1). These allow comparison to power targets. Table 1 and Table 2 show that, based on our power-analysis tools, we have calculated 3.5 W, 5.5 W, and 7.0 W for the three FPGAs on our board. The estimated total power for the FPGAs is 16 W, and that of the ASIC and DRAM are 10 W. This totals out to 26 W, which exceeds our budget of 20 W. This is the point where we must learn what consumes power in the FPGA, and what methods of optimization may be available.
Power Consumption In FPGAs
There are two primary areas of power consumption in FPGAs. Static power comes from transistor leakage, and dynamic power comes from voltage swing, toggle rate, and capacitance. Both are important factors in meeting a power budget and power optimization. Therefore, it’s important to know what each factor is and how it varies with different operating conditions.
Static Power And Its Variation With Process, Voltage, And Temperature: Static power is now significant at 90 nm for both ASICs and FPGAs. To boost transistor performance, one needs to lower the device’s voltage threshold (VT), which also increases leakage. Leakage of the 90-nm transistors varies strongly with process, because the VT of the transistors varies due to doping, and the gate length varies due to lithography. This can create larger changes in transistor speed and leakage. Reduced VT or gate length both increase leakage and speed, while the converse is also true. The variation in leakage and static power is about 2 to 1 between worst-case and typical process.
Leakage and static power are also influenced strongly by core voltage (VCCINT), with variations that go approximately as the square and cube, respectively, of VCCINT. Static power shows about a 15% increase with only a 5% increase in VCCINT. Leakage is also very strongly influenced by junction (or die) temperature (TJ).
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