It was a steamy morning in late July when I drove into Manhattan for a breakfast meeting with Chuck Byers of TSMC and Anna del Rosario of Altera. Ostensibly, the meeting was to discuss TSMC's ongoing manufacturing partnership with Altera.
Because I had an upcoming Technology Report on my plate on the subject of design for manufacturing (DFM), I decided to pick Byers' brain a bit. Chuck's first comment on DFM was to remind me that the "D" stands for design. "DFM is a design problem," said Byers.
This got me thinking: If DFM is a design problem, perhaps I should approach my report from that standpoint. What, if anything, can front-end designers do with today's EDA methodologies to positively influence their designs' manufacturability and yields? That premise guided me in my interviews for this story.
I had my first conversation with Cadence. Upon explaining my angle for this story, Mark Miller, Cadence's VP for DFM business development, said that there are two ways to define DFM. "There's DFM as it is," said Miller, "and there's DFM as it should be."
THE STATE OF DFM
DFM "as it is" consists largely of traditional physical verification, optical-proximity correction (OPC) and reticle-enhancement technologies (RET), and some mask-data preparation. "It's a lot of reactive behaviors after the design has reached what we used to call signoff," says Miller.
Why is DFM necessary in the first place? It's mostly because at sub-nanometer geometries, the structures being printed in the fabs are smaller than the wavelength of light they're printed with. Current 193-nm steppers simply don't have the resolution to accurately render what was drawn by the designer. The shapes of the structures represented in the GDSII are distorted in the lithography process; thus they often require correction via OPC and/or RET techniques (Fig. 1).
What, then, should DFM be? Clearly, if it mostly comprises efforts to compensate for the steppers' inability to resolve the microscopic structures intended by designers, that's not design for manufacturing. For Miller, what DFM should be is "anticipating and compensating for mechanical, electrical, and lithographic process attributes and variations during the design phase."
While intriguing, Miller's comments weren't quite what I was expecting. Neither Miller nor David Thon, Cadence's DFM marketing manager, ever got around to how designers themselves could directly influence yield.
Yet Miller and Thon did point me in an interesting direction, one that proved to be a persistent theme in subsequent discussions. "When you talk to TSMC again, ask them about the Group 2 manufacturing advisory rules and 90-nm and below rule decks that they're building," said Miller.
Foundries such as TSMC have two sets of design-rule checking (DRC) for incoming GDSII. "In the good old days," said Miller, "they just gave you a DRC deck. Now this second set of rules has been added to the puzzle. They're not pass/fail rules, but rules centered around ranges of values."
The implication of the Group 2 rules, said Miller, is that the foundry is pushing the onus for manufacturability back onto the designer. "They're saying, we guarantee we can make you one of these. But because of variations and distortion factors, you may get a range of values for various parameters," said Miller.
Next, I spoke with Sameer Patel, senior director of the Design Implementation Business Unit at Magma Design Automation. He described the differences between manufacturability catastrophic (short and/or open circuits) issues and issues related to parametric (or statistical) variation and reliability. Examples of parametric variation may include capacitance or resistance increases that affect timing but don't necessarily cause total failure.
Some defects are related to random particles. Sometimes they're extra ones, and sometimes they're missing. There's little designers could possibly do to minimize these.
Others are systematic defects. These are akin to the processes that go into chipmaking. Lithography problems, such as the steppers' lack of resolution, fall into this category, too.
Processes like chemical/mechanical polishing (CMP), used to planarize the wafer, can cause substantial variation in interconnect thickness across the wafer and even the die.
When designers model their interconnects, they usually assume a constant thickness. At the pending 65-nm process node, CMP is apt to cause variations in interconnect thickness, and hence in resistance and capacitance, of up to 40% versus what they modeled.
A third classification of defects is the "unknown" type. Generally related to process variability, these effects simply can't be known or determined during the design cycle, making them nearly impossible to model or anticipate. They're usually parametric variations that will affect timing and must be addressed after layout.
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