The push for 3D packaging of semiconductor ICs directly results from market demands for smaller and lower-profile, lighter, and lower-cost packaged ICs that consume less power. With such market forces at play, package designers are feeling the strain to keep pace with their IC chip designer brethren.
For several decades, IC designers could leverage the advantages of a silicon die's planar area (the X and Y directions) to define and pack in more transistors and gates. Getting the most functions possible on a single planar piece of silicon is the everlasting goal for IC designers. That model is changing, though, and it's often a myth for many consumer electronics applications.
As line geometries shrink to 40 nm and beyond, critical issues like higher costs and a greater need for thermal management raise their ugly heads. Moreover, the development of system-on-a-chip (SoC) ICs packed with ever-more functions on a single planar chip is becoming prohibitively expensive. Thus, there's a push toward leveraging a silicon die's third dimension, the Z axis, to satisfy mass-market applications in the consumer, automotive, and medical electronics fields, particularly for portable devices.
During the 1990s, small-footprint IC package creation began with the development of the thin small-outline package (TSOP), followed by the chip-scale package (CSP). The last few years have ushered in multichip packages (MCPs) and system-ina-package (SiP) concepts (Fig. 1). An MCP holds two or more IC die in one package. An SiP combines an IC die with other components in a single package.
Though MCPs and SiPs constitute a small part of the overall IC package market, they're growing in market share. Market research firm IC Insights says MCPs will grow at a compound annual growth rate (CAGR) of 12% through 2009, and SiPs will grow at a CAGR of 14.6% through 2009. These growth rates exceed the general growth rate of all IC-package types.
The cell phone is the most significant 3D-packaging application. Nokia expects an annual 20% drop in weight and overall size for cell phones over the next few years, ratcheting up the pressure. The company also predicts the overall number of cell phones worldwide to expand to 740 million units by year's end, compared to 643 million units last year.
Digital cameras, another major driver for 3D packaging, use the SiP approach. "Key technology drivers for the SiP approach are the use of x32 double-data-rate (DDR) memory devices with high-speed buses, an increase in memory capacity, and the integration of all-memory chips with logic for lowend products," says Tom Gregorich, senior director of IC package engineering for Qualcomm.
Other consumer electronics applications for 3D packaging include digital camcorders and DVD players. A number of consumer electronics items employ the CSP approach. In a CSP, silicon dies are stacked on top of one another within a single package. The dies contain memory devices such as flash and static RAM, as well as logic devices.
A CSP performs at a higher level than the previous-generation TSOP. It can handle signals well beyond the 400-MHz limit of TSOPs and features shorter signal delays. Tessera has pioneered many CSP advances, such as its m Z ball-stack technology. Up to eight m Z ball-stacks are possible for DDR2-type memory.
Tessera also developed a lowerprofile CSP for RF wireless handsets, which compares favorably to a ball-grid array (BGA) package (Fig. 2). It uses coplanar pins on a compliant substrate, enables the use of 300-mm fine-pitch devices, has improved electrical performance, and doesn't require a testing socket interconnect. Simple pressure contact to the pc board is all that's needed.
DEFINING A 3D PACKAGE
Several notable approaches were made to realize 3D IC packaging. Yet there's some confusion over defining such a package. The 3D purists argue that a true 3D IC package holds a monolithic IC with multiple layers of interconnected silicon devices in the vertical direction.
Such an approach starts from the front end of an IC process. It differs from conventional so-called 3D packages that essentially stack chips and ICs at the back end of a process. Those purists argue that while back-end process approaches may provide small-footprint and high-density advantages, they're challenged by higher costs (due to fewer known-good dies, or KGDs) and thermal-management issues. Front-end-based approaches don't face such challenges.
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