[Product Innovation]
Transceiver Chip Replaces Parallel Backplanes With High-Speed Serial Links
Device hands designers a way to reduce bottlenecks in network and computer systems.
With parallel backplanes plagued by a variety of problems, new serial architectures are poised to take over in high-end network and computer systems. Fortunately, along comes the 21Z01 OctalPHY transceiver, which facilitates the design of high-speed serial backplanes. It can reduce hundreds of parallel backplane pins to a few serial connections. Engineers can use the chip to scale their designs and, according to the company, achieve any level of bus performance by adding as many serial links as needed.
Essentially, the 21Z01 is an eight-channel transceiver chip that takes a parallel bus (input and output buses) and converts it to a very-high-speed serial bit stream. This device from AANetcom Inc. can convert a 160-bit-wide parallel backplane operating at 125 MHz into 16 differential-pair serial connections, each operating at up to 1.56 Gbits/s. Its key functional blocks include a clock synthesizer, 8B/10B (8-bit/10-bit) encoder, serializer/deserializer, clock recovery, byte aligner, 10B/8B decoder, and two FIFO memories.
Figure 1 shows one of the eight channels of AANetcom's 21Z01 broken out into some detail. Ten bits of information come into the device. Actually, 5 or 10 is shown because a user can communicate 10 bits over just 5 pins using a dual data-rate technique. The data goes into a short FIFO and and then moves onto an 8B/10B encoder.
That encoding technique maps the 8 bits of user data into 10 bits that will actually be transmitted. The goal is to eventually recover a clock from the serial data stream by noticing the locations of its transitions. Doing so requires a minimum density of transitions in the data. In other words, the data cannot stay at 0 or 1 forever. The 8B/10B encoding provides that assurance. For every 8 bits of user data, 10 bits of information are created and transmitted. This is serialized and converted from its parallel form to the high-speed serial stream. At its input, the serializer requires a 1.25- to 1.6-GHz clock (not shown).
"It is not a trivial undertaking, of course, to create a clock that fast," says Joel Dedrick, vice president of business development at AANetcom."And we don't ask the user to do that for us. Internally, we have a phase-locked loop that takes the low-speed clock provided by the user and creates the needed high-speed clock that we use to transmit this data."
The differential output is the resulting serial data stream. This can drive either the backplane directly or a fiber- optic transceiver. In the reverse process, the high-speed serial input from another 21Z01 enters the chip through the differential input. The first step is to recover the clock, which means observing the data stream and extracting a clock from it that's suitable for capturing every one of the incoming bits. "The incoming bits at these data rates only last 700 or 800 picoseconds," states Dedrick, "so capturing them into a register is no small feat."
After the capture, deserializing occurs. The serial data converts back to 10-bit parallel data words. Then, the reverse of the encoding process returns to the originally transmitted 8-bit byte of user information. This goes into a FIFO.
The purpose of the FIFO is twofold. The eight channels shown could all potentially be arriving from different sources, thereby coming in at slightly different rates. According to Dedrick, "It's a little bit of a mess for the user to be handling eight streams of data coming in at slightly different clock rates. So we provide, as a convenience, a FIFO that can line all of those data up on the user's local clock and hand them off as one single, 80-bit entity transferred over to the user's local clock domain. That makes the design job on the other side—the chip that sits just to the left of this one—much easier."
Secondly, the FIFOs are needed in trunking applications, such as inter-campus networks. In this type of application, the 21Z01 provides the high-bandwidth trunk between two buildings. All eight channels need to be synchronized so that the data going in one side comes out aligned on the other side.
Even if the propagation delays of the serial media between buildings aren't exactly matched, Dedrick points out that the user still expects the data that went in together to come out together. The FIFOs actually have a trunking mode that allows them to cooperate with each other and make sure that the data comes out lined up correctly.
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