It hasn't been a banner year for the EDA industry. For one, growth is flat throughout the industry. The state of EDA technology is a major concern among many designers. Even though leading IDM and merchant-foundries are taping out 65-nm test chips, the big question is whether or not tool support for 65-nm design is really ready.
Among the biggest areas of concern is manufacturability. In our September 29 issue, I painted a less-than-glowing portrait of the current state of what we call "design for manufacturing," or DFM (see "The Truth About Design For Manufacturing," Sept. 29, 2005, p. 47, ED Online 11130). It's not that EDA vendors don't care about the issue or that they aren't trying. In truth, so much of what's being called DFM really isn't that at all. Most of it has little or nothing to do with the design side of the equation. But despite my earlier gloomy assessment, glimmers of hope for real DFM—actual design for manufacturing— have surfaced during 2005.
Most of what passes for DFM lies in the realm of reticle-enhancement technology (RET) and/or optical proximity correction (OPC)—not that there's anything wrong with either. In fact, without them, a lot of 130-nm tapeouts would never happen.
This year, Aprio Technologies launched its Halo suite of RET products. Aprio offers the right idea about RET and DFM in general: moving manufacturing data into the hands of designers. That's been the missing link in terms of what constitutes real DFM. Aprio's reconfigurable approach to RET makes it essentially an incremental technology—something sorely lacking within the industry. The result is greatly diminished runtimes for IC respins or engineering-change orders.
For DFM to take off, there must be a shift in emphasis from rule-based approaches to a model-based paradigm. Ponte Solutions unveiled a promising technology that will leverage statistical process-based yield models to deliver design-stage yield analysis and prediction. Rule-based approaches reflect neither process variations nor design specifics. A model-based methodology reflects both. It correlates to foundry process data.
A huge amount of guesswork is inherent in IC manufacturing. One of the largest contributors to this issue is the chemical-mechanical polishing (CMP) step that wafers must undergo to ensure planarity. CMP removes some of the top-layer metal, and as a result, interconnects end up with electrical characteristics that are very different from their initial designs. Praesagus launched a DFM platform that lets designers predict these variations in copper interconnects. With predictions in hand, they can verify manufacturability before committing to fabrication of test wafers.
Perhaps the real future of DFM lies in building up an exhaustive body of knowledge about process technology before design even begins. That takes us into the realm of technology CAD, or TCAD, tools. Synopsys' Sentaurus TCAD tool suite, announced in October, provides a means to simulate all aspects of processes, both for purposes of optimization and for identification of potential yield problems that must be addressed in the design prior to volume production. With proper calibration using prototype wafers, TCAD tools can accurately predict how silicon will fare at new technology nodes. The fab line can then be tuned to the specific design, promising higher yields in production.
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