Until recently, integrated-circuit design and manufacturing methods have scaled successfully. They allowed designers and fabs to make incremental changes while continuing to use existing tools. But traditional design methods are running out of steam with today's deep-submicron chips. The demands of system-on-a-chip (SoC) devices with millions of gates have stretched tools' capabilities beyond their practical ability to keep pace with design productivity. Timing verification is just one area in which the limits of today's tools are making SoC design harder, longer, and less efficient.
There's no question that powerful tools are enablers for ASIC designs. But these tools don't yet have the capabilities required for successful SoC design. They don't just need the specification of a complex SoC. The tools also require the communication of that specification throughout the design process. Design and layout tools must be able to integrate well with all of the other toolsets used in the design. After all, improper translation between toolsets can lead to inaccuracies in the final design.
Until recently, the traditional design-flow practices that delay layout and timing verification in the design cycle also hampered the effectiveness of these tools. Still, design teams are often forced to perform numerous iterations before achieving a successful design.
Other problems lie in the verification of the SoC. The chip's magnitude and complexity have made this step both difficult and time-consuming. Today's deterministic, functional verification methods aren't successful in catching corner cases and exceptions, which can have grave effects on the design's overall effectiveness. Most designers get stuck running excessive simulations at the gate level. This takes a great deal of time and computing power. It also makes deterministic, functional-verification methods impractical when trying to meet a time-to-market window.
To solve these issues, many designers are striving for higher levels of abstraction—from the gate level to the register-transfer and C levels. Too many gates exist to be able to simulate and verify each one. Still, each step up the abstraction ladder offers much faster dynamic verification, even though it's at the expense of accuracy.
Timing delays are now predominately determined by interconnect rather than gate delays, however. So timing is heavily influenced by layout. Interconnect capacitance can be estimated before layout, but only the final design will reveal actual capacitances and related delays. Designers accept the need to intervene manually to fix some timing problems. But even if the interconnect estimates are 99.99% accurate, a large number of errors will still require such intervention in a million-gate design. A large chip simply has too many timing paths.
To overcome some of these difficulties, the design team and the tools they use must employ a hierarchical approach to the design process. In the flat design approach, all of the blocks of a chip, as well as the interconnects within and between those blocks, are physically constructed as one large component. Any changes required could cause a rippling effect.
Often, modifications to block A may impact the timing performance of block B. Fixing block B can then cause a problem in block C, and so on. Not only is this harmful to the overall design productivity. It also means that no part is finished until the entire design is complete.
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