[Design Application]
Quad-Data-Rate SRAM Subsystems Maximize System Performance
The latest-generation QDR SRAMs couple with an FPGA controller to send performance skyward.
Demand for higher-speed systems is a direct result of the Internet boom. RISC CPU speeds are hitting clock rates of 500 MHz and beyond. But static-memory subsystems are still hard-pressed to keep pace, even with the appearance of double-data-rate SRAMs.
One of the quicker solutions is to implement a memory subsystem that employs the latest quad-data-rate (QDR) SRAMs. These memories provide a high-performance architecture targeted at the next generation of switches and routers, which operate at data rates above 200 MHz. Compared to existing memory solutions, QDR SRAMs are expected to greatly increase system-memory bandwidth as well as serve as the main memory for lookup tables, linked lists, and controller buffer memory.
The architecture that they employ enables chip performance to surpass that of existing solutions. Data throughputs of 11.592 Gbits/s are possible. That's about four times the performance of comparable SRAMs in today's market. The QDR architecture was jointly developed by Cypress Semiconductor, IDT, and Micron Technology.
As with any new architecture, the supporting circuits that control it and interface to it are few and far between. Programmable-logic devices, most notably field-programmable gate arrays (FPGAs), can be used to fill the breach. They implement the control and interface logic required to tie CPUs to QDR SRAMs. To understand better, examine the design of a QDR SRAM memory controller that's based on a high-speed FPGA from Xilinx.
Before going into it, though, look at the use of SRAMs in data-communication systems. Initially, they were put to work as data buffers, link-list tables, and pointer tables. The reason was that they allow fast, low-latency access to memory.
Networking applications usually obtain their high bandwidth by having extremely quick memory access. Because of that, they've always used the fastest available SRAMs. Most applications started with asynchronous SRAMs. These SRAMs operated in the 10- to 15-ns speed range.
As demands on networking systems began to increase, applications used the next-best available memory, the pipelined-burst SRAM (PBSRAM). With these SRAMs, networking applications operated with a higher bandwidth, and they simplified the interface by employing synchronous transfers rather than using asynchronous control.
PBSRAMs were optimized for PC cache applications, however, in which access to the memory is dominated by reads with very few writes. That way, wait states between reads and writes don't limit the performance of the caches. Networking applications typically have equal amounts of reads and writes to memory, so PBSRAMS could only offer limited incremental performance.
This limitation led to the development of no-bus-latency SRAMs (NoBL SRAMs). Similar to the zero-bus-turnaround (ZBT) devices offered by other SRAM suppliers, the modified architectures allowed networking applications to operate without any wait states between reads and writes.
NoBL SRAMs enable the complete use of memory bandwidth, which significantly improves the bandwidth of networking applications. The QDR architecture was developed to further improve the interface's bandwidth. It also overcomes several limitations of PBSRAMs and NoBL SRAMs.
The QDR SRAM has separate input and output ports for read and write. Although those ports share address lines, separate differential clocks exist for the input and output ports. Data can be transferred using double-data-rate (DDR) protocols on both input and output ports. Four words can be transferred on every clock cycle: two in and two out of the device (hence the name quad data rate).
These SRAMs are currently available in two types: QDR2 and QDR4. The difference between them is the number of words of data that can be obtained from the memory on a single read or write. The QDR2 provides two words of data on a single read, while the QDR4 provides four. The consortium (Cypress, Micron, and IDT) will support both the QDR2 (Cypress' CY7C1302, Micron's MT54V51218E, and IDT's 71T628) and the QDR4 (Cypress' CY7C1304, Micron's MT54V51218A, and IDT's 71T648). The basic block diagram of the Cypress CY7C1302 consists of a 512-kword by 18-bit memory array with separate pins for input and output data (Fig. 1). The address lines are common for the read and write ports. Separate clocks are provided for the input and output ports.
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