In a perfect world, fabrication of silicon ICs would be a perfectly predictable process. Not only would every chip be absolutely identical, but there would be no variations from wafer to wafer, or lot to lot. In such a paradise, all chips would meet their predicted design parameters. They would all run at the designers' intended speed, no faster and no slower. All would meet their timing specifications. There would be no clock skew, no IR-drop surprises, and happiest of all, no need whatsoever for pessimistic design approaches.
But we don't live in that perfect world. Trains and planes don't run on time. New cars almost never get the mileage claimed by their makers. And silicon fabrication processes vary, sometimes wildly, and in ways that are maddeningly unpredictable. Circuits can vary from predicted physical values in a number of ways, ultimately affecting the transistors themselves, the wires that interconnect them, or both.
Designers have faced the variability of fabrication processes since day one, and by various means, manage to get around it. Primarily, it's through static timing analysis. But a new generation of static timing analysis is upon us, one that uses statistical techniques to overcome the issues inherent in traditional static techniques. In this report, we'll look at where static analysis has been and where it must go to cope with the complexities of nanometer silicon technologies.
CORNERING COMPLEXITY
Traditional static timing analysis (STA) is, and has been, the method that virtually every digital design team uses to achieve timing signoff. In STA, you must have a timing model for every cell in your design (or at least the signal paths you care about). The analyzer uses those timing models to calculate delays for all cells in a given path. Those delays, in turn, are summed to determine total path delays.
Process variability comes into play here. With the move downward in process geometries, the variability in silicon or, more precisely, the ability to account for it becomes the priority in maintaining the designers' intended performance.
"If you look at SiO2; (silicon-dioxide) thicknesses, for example, we're talking about 14 atoms or so in today's high-end processes," says Leon Stok, director of the electronic design business for IBM's Systems and Technology group. "If you're off by one or two atoms, you're suddenly off by 10% or 20%. Before, this wasn't an issue. We think we're seeing the limits of some of the physical phenomena we tend to deal with."
You may intend for your design to run at, say, 500 MHz. But with the various process variability factors involved, even if we assumed that all of the chips were functional, not all of them will run at your target speed. Some may run at 400 MHz, some at 450 MHz, and even some at 550 MHz.
This is why "corner-based" analysis has been the mainstay for many years. The essence of corner-based analysis is to determine the best and worst cases for various parameters, such as ambient temperatures, supply voltage, and many others. Each of these parameters is referred to as a "corner."
While corner-based analysis continues to be indispensable now and into the foreseeable future, it does have several disadvantages. For one thing, it's slow. At nanometer geometries, the number of corners is exploding. At larger geometries, designers could get away with analyzing worst-case parameters for just a handful of corners. Today, designers find themselves analyzing 64 or more corners over a full range of process variation. That translates into a huge runtime burden.
And that's just the inter-die, or die-to-die, variation. There's also on-chip variation (OCV) to consider. "OCV effectively adds some pessimism to the design through the analysis to cover a variation that could happen between, say, the clock routes between devices that are spread around the chip," says Robert Jones, senior director of Magma Design Automation's Silicon Signoff Unit.
Consequently, between interdie and intradie variations, corner-based analysis is quickly becoming a millstone around designers' necks. Yes, it's slow and cumbersome. But perhaps even worse, it compels design from a pessimistic standpoint.
When designers are forced to consider all of the worst-case corners they've analyzed, they suddenly find out their analysis predicts that some of their 500-MHz chips may only run at 350 MHz. Thus, to optimize the yield that will run at 500 MHz, they'll compensate by overdesigning.
"Corner-based design is perceived as leaving a lot of quality on the table," says Andrew Kahng, co-founder and CTO of Blaze DFM. "People are very worried about the return on investment (ROI) of the next generation of silicon technology. As guardbanding increases, obviously you're harvesting less of the potential ROI of that process improvement. At some point, if this isn't better managed, the ROI will just not be there."
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