[Design View / Design Solution]
Rail-Signoff Analysis Ensures SoC Power Integrity
By starting power-integrity planning and analysis early, you avoid many problems that are difficult to correct in the later stages of the design flow.
More than ever, power integrity is vital in the successful creation of today's system-on-a-chip (SoC) designs. That's because e xcessive rail voltage drop ( IR drop) and ground bounce can create timing problems. Also, excessive current can cause electromigration and related thermal effects, leading to chip failures.
The first steps designers must take to prevent these problems are solid power-network planning and implementation. The next step is a good rail-signoff analysis flow to ensure that all power-related issues are resolved. To avoid timing problems and device failure, designers need to analyze an SoC's entire power network to ensure that it provides adequate power integrity.
Obtaining accurate rail analysis requires a good methodology and practical guidelines that expedite the flow. These guidelines include practices such as screening library exchange format (LEF) and design exchange format (DEF) files , creating white-box representations to speed analysis, obtaining toggle-rate information for power analysis, and using electromigration plots to identify IR-drop issues.
While dynamic IR-drop effects also should be considered due to the smaller margins of sub-130-nm processes in the overall SoC power closure, this article provides an overview of a suggested rail-signoff analysis flow for static IR-drop analysis.
Rail-Signoff Overview IR drop occurs due to the resistive nature of the power routing from the power pads to the cell instances in the design. IR drop for a given instance depends on the current delivered by the power network, which should enable cells to operate at their targeted frequency in that area of the design. Considering these two factors, the IR drop across the power network will vary across the design. With the transition to smaller process geometries, IR drop is even more critical due to increased wire resistance and self-heating introduced by interconnect technology scaling.
Another problem, electromigration, may occur for several reasons associated with the current flowing through the power rails. Excessive current density over a long period of time, as well as the high power requirements of high-frequency designs, can lead to electromigration unless care is taken in designing the power network. Electromigration analysis is very important since, if left undetected, electromigration can cause performance degradation and chip malfunction over time in products already shipped. Like IR drop, electromigration is a growing problem in finer process geometries.
The suggested signoff flow analyzes IR drop and electromigration in large SoCs (Fig. 1). It was proven effective in a service project for five complex HDTV SoCs. The primary goal was to keep the flow implementation simple for ease of use across multiple designs and processes. A comprehensive pushbutton flow was not developed, as we considered it is unrealistic due to the many complexities of today's designs and libraries.
The flow requires only standard DEF and LEF for physical design and library input. Because the flow is standalone for rail signoff, it works with many third-party place-and-route tools. To allow for fast analysis spins late in the design cycle, the flow setup has two parts: reference library preparation and design library preparation (Fig. 2).
With this setup approach, you create all reference libraries only once in an SoC project. Then, you can execute fast iterations on the design-library creation and subsequent analysis each time you make design changes. Note that some library vendors provide Liberty files for only min and max corners. However, it's best to have min, nom, and max corners available so you can analyze more operating-condition (PVT) combinations.
Running The Rail Signoff Flow To run the first part of the suggested flow, an average power analysis, you should set variables for VDD at a maximum, worst-case (max) synthesis library and worst-case (c_worst or max_c) signal net parasitics. The flow chart in Figure 3 shows the suggested steps in this part of the flow.
When using the flow's clock-domain-based toggle method, you can set all signal nets in the target domain to toggle once every other clock, for an equivalent 50% toggle rate. Some tools, such as the rail analysis tool Astro-Rail, can define a 100-MHz clock at the top level and automatically propagate it through the design hierarchy.
This way, all signal nets in the design take on appropriate toggle rates based on statistical estimations. For example, a simple 20% toggle rate ?per unit time? for this 100-MHz clock can be computed using the following equation (in which a toggle consists of two edges per 10-ns clock period):
TR = (0.20 × 2)/10.0 ns = 0.04
The analysis tool estimates power consumption for hard macros based on the toggle rates of their input ports. But you can improve accuracy by gathering power information from the macro data sheets and annotating it on the hard macros.
After power/ground net extraction (Fig. 4) come the IR-drop and electromigration analyses that are the heart of rail analysis (Fig. 5). Experience has shown that two different sets of variables provide the best scenarios for these two analyses. While the IR-drop analysis uses worst-case timing conditions (worst parasitics, slow synthesis library, high temperature, and nominal VDD), the electromigration analysis requires a hybrid condition (worst parasitics, fast synthesis library, high temperature, highest VDD ). To determine the worst-case impact on device performance due to collapsing supply rails, it's useful to modify the recommended IR-drop operating conditions. Use the worst-case, or lowest, VDD .
Far and away the best technical article I have ever read in my entire life. The fact that David is my son has no influence on my opinion, of course. Jerry Stringfellow
Jerry Stringfellow -January 19, 2006
Far and away the best technical article I have ever read in my entire life. The fact that David is my son has no influence on my opinion, of course. Jerry Stringfellow
Jerry Stringfellow -January 19, 2006
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