[Technology Report]
It's Evolution, Not Revolution, For PCB Tools
To conquer ever-stiffer challenges, pc-board design tools must perpetually evolve-particularly in the high-speed signal realm.
When it comes to pc-board (PCB) design, change isn't necessarily radical. Though IC design tools must keep pace with fast technological changes, tools for the PCB designer tend to embrace change in a more evolutionary style.
That's not to say the PCB designer's world is peaceful and calm. Thanks to innovations such as multigigabit serial data-streaming technologies like serializers/deserializers (SERDES), PCB designers face extremely difficult signal-integrity challenges. If their toolsets aren't up to speed (pun intended), they'll likely struggle to meet timing requirements.
All of the above—combined, of course, with the ongoing trend toward higher pin counts on ICs—creates an environment where PCB designers must have the right tools for the task at hand. Even still, that task may catch you by surprise. In this report, we'll survey some of the challenges facing PCB designers and examine how today's crop of design tools handles them.
THE NEED FOR SPEED "PCB design has become a highly constrained, complex system design process," says Werner Rissiek, Zuken's European general manager of engineering. "It's definitely not simply about artwork any longer. It's engineering all the way through from specifying your product schematics to floorplanning, layout, and manufacturing."
Today, extremely high signal speeds drive much of that need for engineering throughout the board-design process. Modern processors require modern buses, and those buses carry very fast signals. "Once clock rates hit 300 or 400 MHz, you start to really struggle with signal integrity," says John Isaac, director of market development for Mentor Graphics' System Design Division.
Migrating from parallel buses to serial data and clock transfers exacerbates the high-speed signal trend. For example, the PCI Express protocol has largely replaced the PCI bus. PCI Express replaces a parallel bus with a differential pair that transmits data and clock on the same link.
"There are two benefits to such schemes," says A.J. Incorvaia, vice president of research and development for Cadence's Allegro PCB products. "One is that you take a lot less PCB real estate to design in the links. Also, being differential, the links are somewhat immune to interference from aggressor nets. They're somewhat shielded because interference on both lines cancels out."
The design challenge is the 2.5-Gbit/s rate imposed by PCI Express. At such speeds, signals are much more sensitive to path discontinuities like vias, connectors, or long traces.
"Designing a complete interconnect is a big factor in success," says Incorvaia. "Most often, people have to simulate to figure out what the design rules are. Then, designing the interconnects based on those constraints is a challenge."
One example of a simulation tool that can handle high-speed challenges is Cadence's Allegro PCB SI 630 (Fig. 1). It simulates up to 10 kbits/s and 1 Mbit/hour on a desktop PC, which means it can run through multiple full-board simulations in a single day.
"Channel analysis is the key," says Incorvaia. "We have innovative ways to characterize the channel and simulate that in a non-traditional way."
Another speed-related issue making life difficult for PCB designers concerns memory access. Circuit designers are seeing a move from standard SDRAM to double-data-rate (DDR). Current designs mostly use DDR2 memory. With access rates of 800 MHz, though, DDR3 continues to gain favor in consumer electronics.
"When you go from DDR to DDR2 and DDR3, designers need detailed simulation to come up with the design constraints that will enable them to do layout according to those constraints," says Incorvaia. "Otherwise, you design a board and run into iterations."
Broad adoption of high-speed serial buses and advanced memory technologies forces board designers to become experts in signal integrity, and that may not necessarily be the case for many of these designers. In fact, the concerns at these speeds may go above and beyond simple signal integrity.
"High-speed considerations are changing from signal integrity, where you look at characteristics like overshoot or the delay for just one signal, to datastream verification," says Zuken's Rissiek. "Here, you are no longer interested in a single effect on a single signal, but rather multiple signals and their sequence through components. You need to ensure that the datastream is reliable. So you need eye diagrams as well as complex stimuli for analysis that reflects a real datastream on the signals."
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