[Ideas For Design]
New Design Tools Can Make Your Analog Layouts "Shape Up"
Shape-based routing has significant advantages for time-to-yield and design-for-manufacturing for analog, mixed-signal, and embedded memory designs.
There is no doubt that the challenge of designing analog integrated circuits gets more intense every day. Market demand and price pressures for end products reduce the design time . Add to that demanding performance and frequency requirements and burgeoning manufacturing issues and you have a potentially volatile mix. Although there' s plenty of ?time-to-market? talk, an increasingly important metric is time-to-yield. As a result, the analog portion of a design becomes critical to meet these target s.
Many analog devices are still routed by hand, relying on the experience of analog designers to produce the most cost- effective layout. Engineers will spend months tweaking a design to optimize the layout for maximum yield. And they will trade off many revisions of a mask set, costing millions of dollars, just to get a one percentage point increase in yield.
Now, there's a big push toward automated design tools, particularly in routing, that can produce similar levels of performance in a fraction of the time. Using an automated tool can reduce the time to route a typical analog chip from three months for designs done by hand to three hours, and shrink die size by 30%.
Minimizing the time-to- yield means getting the design right as quickly as possible. T hat doesn't simply involve creating ultra-fast design tools, though. It' s more important to cut down the amount of iterations, as well as reduce each iteration's number of data-transfer cycles between tools.
Since many capabilities are accessed from one tool, it's vital to check all the rules that pervade it. That way, designs become more accurate as they progress through the flow, reducing and/or eliminating iterations.
These issues aren't just relevant for pure analog chips. Many, if not most, large chip designs have some element of mixed-signal design, whether through analog interfaces, or analog parts of digital subsystems ( such as high- speed buses, power management, internal voltage pumps, phase-locked loops ( PLLs), and non volatile RAMs) .
Grid-Based Routing Most routing tools today use grid-based algorithms, which take a completed design and break it up into a grid of small squares in a database. Areas of the grid containing components are blocked out. T he wires are then routed along the grid lines to link up the design's components, using the number of squares in the grid to determine the minimum path for routing. Because t his technique is so memory intensive, the majority of the design data (types of components, potential wire interaction) is dropped from the routing database.
To accelerate these grid-based routers and lower the memory requirements, it's best to use global routing. Instead of breaking the design into a very large number of wire-grid squares, it' s broken into a smaller number of larger squares, each with sides equal to many wire pitches. Due to the size of these squares, the router really can't consider the detailed positioning of the interconnects. However, the squares can solve global problems such as congestion. Once the global routing is complete, the wire-grid approach is used to join up the pins and edges of the global routing grid, one at a time.
This technique allows for very rapid routing of multimillion-gate designs and benefits from the falling cost of PC memory and greater PC-processor performance. But it suffers from two main problems, particularly for analog designs.
The main issue is that there' s no data on which other nets are around the net being routed. Therefore, controlling the interactions between different classes of nets (e. g., analog and digital) or managing signal-integrity issues is difficult. The grid may also force the wires to be at a non-optimal pitch (due to the requirement to via between layers where they have common grid points) . Leaving space for vias, even in areas that don't need them, can lead to an inefficient and costly layout. And, the rigid grid makes it costly to increase the spacing between nets to solve signal-integrity issues.
Shape-Based Routing Utilizing alternative approaches to traditional grid-based routing algorithms can be very beneficial, improving a design's time-to-market and time-to-yield. Shape-based routing has been around for many years in board design. Now its strengths in area efficiency, signal integrity, and yield improvement?for analog and mixed- signal designs in particular?are driving its use in chip design.
The basic algorithms were originally developed at pc-board tool vendor Racal-Redac (now Zuken) in the 198 0s. These don't use an abstract grid, but create a ? flood? in one direction until the flood reaches an obstruction (Fig. 1). An unobstructed ? edge? in the direction of the target is found. Then t he algorithm floods in that direction until it reaches another obstruction. T he process repeats until it reaches the tar get.
Each edge is assessed not only for the distance it takes, but also for factors such as parasitics and signal integrity. This adds much more flexibility to the technique. All assessment s are tracked throughout the run, since one direction of exploration may end up in a dead end or in an undesirable route. But a previously unfavored edge may result in a more optimal overall route. (The technique is also coupled with ?rip up and re-try?). In this scenario, the calculation takes into account a path that causes an error.
Because the real shapes of objects are used, tracks can be placed as close as possible to obstructions. This results in a more compact routing pattern. It also factors in yield and process information, particularly for optical proximity correction (OPC). And because the net associated with each object is known, more powerful rules can easily be applied to control the spacing from those objects. So, for instance, the spacing between an analog and a digital nets can be larger than that used between two digital nets. This can dramatically improve the end design's yield.
To get the most efficient routing the first time around, a wide range of data can be used in the routing process, comparing one specific path against design rules and constraints. This eliminates going through the many iterative cycles of routing and post-processing necessary with the grid-based approach.
Using the detailed connectivity information with the true shapes means ?push- aside? techniques can be used, rather than going a long way around or creating an error. T he routing algorithm identifies areas where it could pass simply by moving an existing wire out of the way. This produces shorter wires with fewer vias, as well as an overall higher routing efficiency. The result is smaller, more cost-effective designs. This approach to routing also allows the tool to spread tracks apart to reduce capacitance and make tracks wider to lower resistance (Fig. 2).
Both techniques help reduce RC delays and enhance timing closure. T he key is that these steps happen during the routing process, rather than afterward in a separate tool. As a result, designs are routed correctly without iteration. This can' t be done in grid-based algorithms because the change of width or space will often require tracks to move over a whole extra grid pitch, leaving a much larger than necessary space.
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