Design rules and Spice models continue to be the primary vehicles used to communicate semiconductor manufacturing -process information. Development of rules and models is accomplished via electrical measurement of simple test structures, technology-computer-aided-design (TCAD) modeling, and simulation and optical measurements. Yet, the semiconductor industry acknowledges and accepts the fact that at process technologies of 100 nm and below, these rules and models insufficiently capture process capabilities and limitations. This leads to a disconnect between expected model yields and the yields we actually obtain.
Semiconductor manufacturers realize that “solving” the yield problem requires performing comprehensive process characterization and provision of supplementary data to fab engineers. They could accomplish this by complementing simple test structures with realistic design topologies during process characterization. However, a gap exists between the data that’s available and what the process engineer needs to adequately ramp process yield. Design engineers who are concerned about process issues impacting design performance face this same gap.
Why does this gap exist? A primary reason is that the fab cannot envision all of the different topologies contained within a design. By nature, the fab’s view is “process aware” but not necessarily “design aware.” Another reason is that the amount of silicon required for comprehensive design-aware process characterization using traditional techniques is prohibitive. And finally, the scribe lane—the area on the wafer that houses process monitors—is becoming smaller while the number of parameters that require monitoring is becoming larger. All of these factors make it increasingly difficult for the fab to effectively collect and deliver needed process information.
Even if these issues are resolved by applying brute-force techniques, such as throwing manpower and silicon at the problem, it’s not in the best interest of the fab to provide raw data to process, yield, and design engineers. In the foundry model, the fab hesitates to supply this data because it contains trade secrets. Even in the integrated-device-manufacturer (IDM) model, the voluminous nature of the raw data tends to reduce its value. As a result, a gap exists in the “process intelligence” provided to process and design engineers. The fab should deliver intelligent analysis results and models derived from the process data.
Silicon intellectual-property (IP) products are emerging to help bridge this gap. In one case, a new product’s highly compact test vehicle enables the fab to generate an order of magnitude more data utilizing the same area on the test reticle. This larger data set can include statistical characterization of a device’s performance, process window characterization of a device type, and a large set of design topologies. With such a tool, a process engineer can extract additional “process intelligence” and create comprehensive process models.
Similarly, new silicon IP has also been ported onto the scribe lane so that the fab can monitor a greater number of process parameters. The fab and fabless operations can then do an apples-to-apples comparison of in-production parameter values to those acquired during process qualification. Designers and product engineers can use this “process intelligence” to better calibrate process models.
Information delivered by design rules and Spice models is no longer sufficient for ramping yields at sub-100 nanometer process technologies. A new generation of products, including specialized silicon IP, is required to provide process and design engineers with the comprehensive “process intelligence” needed to manage yields and design performance.
Reprints
