The system-on-a-chip (SoC) era has reached the point where the assembly of such large, complex chips seems almost rote. From a high level, it would appear to be a formula process: choose a processor, choose a bus, bring together your memories and various peripherals, and that's about it. But integrating semiconductor-intellectual property (IP)—the large functional blocks that comprise these various major elements of an SoC—can indeed be a very daunting task.
When contemplating what steps to take to simplify IP integration, three things come immediately to mind. For one, it certainly helps if IP is packaged and described in a standardized fashion. Then the broadest possible range of EDA tools can readily accept it and be able to transfer those descriptions across the design flow. For another, IP blocks must be able to communicate with each other in the system context. Lastly, the quality and pedigree of IP blocks is critical to design engineers (see "The Benefits Of Quality IP" at ED Online 12299 at www.electronicdesign.com).
In this article, we'll take a look at these aspects of IP integration. There's been movement of late in the standards arena, as well as an upsurge in IP quality. We'll look at the activities of the key organizations attempting to bring about industry consensus on IP standards. New choices abound in terms of tools, methodologies, and architectures for the interconnect, which is the lifeblood of an SoC. We'll also look at IP from the perspective of an implementation flow and the special challenges it can pose (see "IP From The Implementation Perspective" at ED Online 12300).
THE IMPORTANCE OF STANDARDS
In any industry, standards lend consistency to the proceedings. Having everyone speak the same language, and use the same terms and concepts to describe the fundamental building blocks and processes that go into putting a product together, is of inestimable importance.
"Using standards gives you confidence that any IP you buy works for that standard," says Keith Clark, vice president of technical marketing at ARM. "It's at least been validated against something that's known. There's that natural advantage, as well as the fact that you can hope there's more IP available for any given standard."
IP standards have come a long way since the earliest days of the merchant-IP market, when formats were plentiful and disagreements raged on how IP should be packaged. Much of the progress in IP standards has come from three key organizations: the Virtual Socket Interface Alliance (VSIA), the Open Core Protocol-International Partnership (OCP-IP), and "Structure for Packaging, Integrating, and Re-using IP within Tool flows," or SPIRIT.
All three organizations come at the goal of easing IP integration for designers a little bit differently, but all manage to avoid working at cross-purposes. In fact, in many cases, their respective efforts are highly complementary. Taken as a whole, all three groups' efforts aim to build out a complex infrastructure for IP integration that requires a great deal of cooperation between IP providers, EDA tool vendors, foundries, integrated device manufacturers (IDMs), and, most critically, design engineers (Fig. 1).
Since its inception in 1996, VSIA's mission is to develop the technical standards required to enable the mixing and matching of IP cores from multiple sources. In the words of Gary Delp, VSIA's chief technology officer (and an LSI Logic Distinguished Engineer who's part of the RapidChip team), VSIA strives to "put together a common vocabulary that can be used to discuss, interconnect, and compare IP."
A 2004 reorganization of VSIA saw a structuring around what the group calls "pillars," or working groups. VSIA's IP Quality Pillar recently announced the release of its QIP Metric v2.0, which can aggressively reduce the time typically required to make an IP purchase decision and to integrate the core. The QIP Metric tool is the result of an extensive beta program that involved a number of leading EDA and semiconductor companies.
The metric helps IP vendors and consumers communicate based on an objective foundation. Besides setting up the basis for measuring a core's characteristics against an industry-approved list of attributes, the metric provides a view of the IP vendor's general approach to IP development. This enables a continuous improvement mechanism. In turn, it also levels the playing field for vendors and allows an integrator to evaluate similar cores from competing vendors.
QIP Metric version 2.0 is easier to use than its predecessor, and it's more streamlined. This version also features simpler IP-qualification metrics covering documentation, deliverables, and information specific to the IP integrator, as well as IP development practices. It includes the newly added vendor assessment, too. And, the requirements for soft IP were restructured and revisited.
"We're working with the Fabless Semiconductor Association on extending the QIP Metric to hard IP," says Delp. The hard-IP metric is expected to see a beta release this summer, after which it will be made publicly available. There's also ongoing work on a quality metric for verification IP and software.
TAG, YOU'RE IT
A standardized set of IP quality metrics that's agreed upon across the IP supply and tool chain would go a long way toward ensuring consistency. The next step, according to Delp, is an IP-deliverables checklist. LSI Logic's internal design teams found two major issues to be a constant hindrance in IP integration.
"You spend a lot of time finding all the deliverables and communicating back and forth on making sure you have the right ones and in the right versions," says Delp. "The other problem is getting a license agreement in place. Those things are part of the context and should be simple."
As part of LSI Logic's engagement with both VSIA and SPIRIT, the company assembled a list of IP deliverables and is working with VSIA and SPIRIT to put them together in electronic databook form. Having the deliverables in an orderly format will help engineers to keep track of what's supposed to be there and whether it's there or not.
VSIA and SPIRIT are cooperating to ensure that commercial IP is described in a standards-compliant way. "Another piece of work for VSIA is IP tagging," says Delp. This is the work of VSIA's IP Protection Pillar.
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