The wheels of innovation are spinning at a breakneck pace in the world of NAND flash memories. With storage capacities hitting 16 Gbits, these memories offer the densest storage of any solid-state memory technology. Look fast, though, because further advances in cell structures, circuit architecture, and process technology will soon leave that number in the dust, raising the bar for NAND flash storage capacity and performance.
Today, NAND flash memories are in high demand for image storage in both digital still cameras and solid-state MPEG-4 video cameras. They're also widely used for music and video storage in the latest media players, such as the Apple iPod Nano and the SanDisk Sansa family. Emerging applications portend huge demand for internal and removable storage for image-, video-, and music-capable cell phones, too.
TWO TYPES OF NAND NAND flash devices are available in two main implementations: single-bit-per-cell (single-level cell, or SLC) and two-bit-per-cell storage. Two different schemes are used to store the latter. The multilevel cell (MLC) uses multiple charge levels. The other scheme, called MirrorBit by Spansion, stores two separate charges, one at each end of the transistor gate (Fig. 1).
Samsung and Toshiba—using MLC schemes—offer the highest-capacity monolithic NAND flash chips available today, at 16 and 8 Gbits, respectively. When the MLC cells aren't as stable as desired, the MLC array can be turned into SLC-based devices during manufacturing by disabling the circuits used to create and sense the multilevel charge values.
From an external viewpoint, the SLC and MLC devices have similar interfaces and control signals. Yet the internal differences between the two cell structures make the technology selection an important part of the overall design decision (see "Paying For Double Density," p. 53).
The SLC memory cells use a single charge threshold to decide whether the cell stores a "1" or "0," which makes value sensing a relatively straightforward task(s). But to ensure data integrity, SLC memories typically employ a single-bit error detection and correction (EDC) scheme that can repair single-bit failures in each data byte.
MCL memory cells, pioneered by Intel, take a different tack. They "divide" the stored charge into four ranges by setting up three charge threshold division points, so that the four ranges can be coded into two bits (Fig. 2b). Each charge state has a range span that's about one-quarter the size of an SLC cell.
The smaller charge per bit could make each bit in the cell more sensitive to upsets, which may change the bit values. As a result, to correct multibit errors, manufacturers of MLC NAND chips often embed EDC schemes that are more complex than those used in SLC NAND devices. Such schemes add to the circuitry overhead while slowing down memory-access speeds and data-transfer rates.
ON THE MARKET Intel's StrataFlash MLC scheme and Spansion's MirrorBit scheme deliver two bits per cell. But the memory architectures offered by both companies are NORbased rather than NAND-based. NOR-based flash memories offer full random access to the data, which also means more overhead circuitry.
The extra circuits limit memory capacity to about one-sixteenth that of NAND flash chips for devices with roughly the same chip size. Intel and Spansion are sampling 1-Gbit dualbit/cell devices, while Samsung and Toshiba are sampling 16-and 8-Gbit chips, respectively.
Capacity is the main driving force in the market. Many flash vendors use multichip packaging to further double or quadruple their package capacity. For example, Toshiba is sampling a 16-Gbit solution by assembling two 8-Gbit chips in a package. It can be delivered many months before a monolithic version might be producible.
By making the package pinout compatible with the next-generation device, the multichip solution can be replaced with a future, more cost-effective monolithic chip. At the same time, the next double-density multichip packaged solution using the new monolithic device can be released, thus paving a long-term upgrade path.
The slight differences between each vendor's NAND flash chips (internal architecture and timing/control differences) make it nearly impossible to get a direct replacement for another vendor's chip. At last month's Intel Developer Forum, Intel proposed developing a standard interface for NAND flash devices to eliminate the need to craft custom controllers. It's too early to tell if this proposal will gain any traction with the NAND flash manufacturers.
To hide the differences between NAND flash vendors, companies such as M-Systems, SanDisk, and Silicon Systems designed their own memory controllers with a generic host interface. These controllers can be software-configured to a particular flash memory's characteristics. Or, they might contain a lookup table that lets the company select from a number of known devices.
Such controllers not only contain the basic memory-control interface, they also often include extra EDC capability to ensure data integrity. In addition, MLC devices are usually specified with a guarantee of 10,000 write operations per bit before failing due to wearout (a buildup of charge that raises the transistor threshold so its ON and OFF states are nearly indistinguishable). SLC chips are a bit more durable and often are specified with a 100,000-cycle write capability.
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