[Design View / Design Solution]
Design A Clock-Distribution Strategy With Confidence
Simulation lets you design a transceiver clocking and frequency-planning strategy while making the required tradeoffs between performance and cost.
Clock-distribution devices create multiple copies of a master clock and distribute them to a variety of integrated circuits. They accept single-ended or differential clock inputs and supply multiple single-ended or differential outputs that are divided or delayed versions of the input clock.
A low-phase-noise crystal oscillator (XO) is commonly used to drive clock-distribution devices. Their sinusoidal outputs are then converted to square waves or pulse trains. Clock jitter is caused by statistical variations of the input reference clock and by clock signal processing. Therefore, a phase-locked loop (PLL) often is included to improve output jitter.
A good example of how clock distribution works can be seen in a typical basestation transceiver. In the transceiver, an AD9510 clock-distribution device supplies clocks to components such as analog-to-digital converters (ADCs), digital-toanalog converters (DACs), application-specific integrated circuits-(ASICs), and field-programmable gate arrays (FPGAs), each of which requires a low-jitter clock at a specific frequency and phase. One part of the system may use one logic family, while a different part uses another. Therefore, the clock outputs must support low-voltage differential signaling (LVDS), CMOS, and emitter-coupled-logic (ECL) compatibility.
Of course, the tradeoff between system performance and system cost is one of many challenges faced by transceiver designers. System engineers must decide which components to use in their transceiver design. But generating clocks and distributing them to these components also affects the transceiver's performance.
Figure 1 shows a typical two-carrier W-CDMA transceiver. Complex relationships exist among frequency, phase, and amplitude between the multiple clocks required by the transceiver. Nonetheless, designers still can easily develop a clockdistribution strategy.
On the receiver side, the AD9945 14-bit ADC 2 digitizes a downconverter mixer's output with a 128-MHz intermediate frequency (IF). For optimum performance, the ADC is clocked at 102.40 MHz using a differential LVPECL clock with broadband jitter of less than 300 fs rms. The sampling clock is accoupled via a transformer or capacitors. The ADC output is processed by the AD6636 digital downconverter (DDC), which provides a baseband complex signal from the W-CDMA carrier (I, Q data stream). The DDC requires a 102.40-MHz LVDS clock. This clock is delayed by 0.5 ns relative to the ADC clock. The on-chip multiplier generates a frequency of 128 MHz so that the numerically controlled oscillator (NCO) can frequencytranslate the IF signal to baseband.
The transmitter accepts unfiltered, interleaved I and Q data from two WCDMA carriers. A digital upconverter (AD6633, DUC) performs pulse-shaping, peak-to-average power-ratio reduction (PAPR), and frequency translation of the W-CDMA carriers to a first IF at 19.20 MHz. The DUC requires a 76.80-MHz CMOS clock and outputs complex data at a rate of 76.80 Msamples/s. The ADC and DUC send their output data to an FPGA. The clock-distribution device has an adjustable delay unit, which enables the clock output to be delayed by 0.11 ns to synchronize the transmit path to the observation path. Controlling this synchronization to within 1/64th of the symbol duration allows for sufficient linearization.
The FPGA, clocked at 307.20 MHz, performs digital pre-distortion (DPD). It oversamples the DUC output by a factor of four to generate a complex signal at the same data rate as the ADC. It outputs complex data at a rate of 153.6 Msamples/s, with an IF of 57.60 MHz. This data is the input to the AD9779 dual DAC. The DAC requires a 614.40-MHz clock with a low-jitter differential LVDS drive. Its complex modulation produces a second IF at 96 MHz. Third-order lowpass filters with a 400-MHz, stop-band frequency filter the complex output. The analog filter outputs drive an analog modulator to upconvert from 96 MHz to a radio frequency at 2.1 GHz.
For optimum performance, the 12-bit AD9430 ADC 1 requires a 153.60-MHz differential LVPECL clock with broadband jitter of less than 300 fs rms. It digitizes the downconverted and filtered version of a high-power amplifier (providing the observation path at an IF of 57.60 MHz). This path is critical for accomplishing high-performance digital predistortion. The ADC output is frequency translated to an IF of 19.20 MHz by an NCO built in the FPGA, which supplies a complex signal at a 153.60-Msample/s rate. The 10-bit AD9215 ADC3 monitors the power amplifier's temperature change and feeds it back to adjust the predistortion coefficients. This ADC requires a 30.72-MHz CMOS clock. Finally, a low-jitter (less than 1 ps rms) LVPECL copy of the reference clock is required.
Figure 2 shows the relative delay between the system clock waveforms. Figure 3 shows the spectrum of two WCDMA carriers, centered at 96 MHz from the DAC (a) and 128 MHz from the ADC (b). This example uses the AD9510 eightchannel, 1.2-GHz, clock-distribution IC to demonstrate how system engineers can design the clock-distribution section.
The reference clock is 19.20 MHz. The on-chip PLL synthesizer and external voltage-controlled oscillator (VCO) generate a 614.40-MHz system clock. Eight independent programmable frequency dividers can be programmed to any integer from 1 to 32. Their phaseoffset can add delays in integer multiples of the VCO time period, approximately 1.63 ns in this example. Finally, by taking advantage of the multiple logic families available on this clockdistribution device, the required combination of LVPECL, LVDS, and CMOS clocking output levels for our transceiver is achieved.
Transceiver designers commonly use phase-noise density and timing jitter to define the performance of clocking components. Timing jitter limits the maximum clock frequency in digital systems, the dynamic range of DACs, and the effective number of bits (ENOB) in ADCs. Furthermore, system engineers can estimate the degradation in error vector magnitude (EVM), signal-to-noise ratio (SNR), and bit error rate (BER) that occurs as a result of jitter. This lets them make tradeoffs between the cost and performance of components used in a transceiver. Therefore, calculating the timing jitter at the output of clock-distribution devices is of great interest.
Please refresh the page if you have trouble reading this text.
Search Electronic Design
Email Newsletter
Sponsored By:
Electronic Design UPDATE provides readers with late-breaking news, opinions from industry experts, and timely technology stories. It's a unique opportunity to get your product message in front of engineers, engineering managers, and corporate managers while they're reading about critical information online.
Reprints
