[Technology Report]
Serial EEPROMs Answer Designers' Needs For More Point Storage
Available with a wide variety of interfaces and features, serial EEPROMs deliver nonvolatile memory in sizes from under1 kbit to 1 Mbit.
Traditional NOR- and NAND-type flash memories dominate most designer's minds when it comes to adding megabytes of nonvolatile storage to a system. But many cost-sensitive applications exist that don't need the high capacity or short access times they deliver. Filling the gap and providing a low-cost, small-format solution are bit-serial EEPROMs. These devices allow users to drop anywhere from a few dozen bits to 1 Mbit of nonvolatile storage into any system.
Although initially developed as a simple nonvolatile memory that could tie into a host processor over a two- or three-wire serial bus, serial memories have evolved into feature-rich devices. They come in versions that offer 8- or 16-bit word widths, which are sometimes switchable between organizations. Other highlights include password protection, block-write protection, and multiple access modes, as well as a multitude of other features and interface options to meet evolving system needs.
For most designers, storage endurance has become almost a non-issue. Through improvements in process technology and various types of error-correction schemes, EEPROM suppliers can now offer endurance ratings of anywhere from 100,000 to one million cycles. Guaranteed data-retention times range from 10 to over 100 years.
As many of the applications are in handheld, battery-powered systems, these serial EEPROMs must be physically small and consume next to no power. Long gone are the days when an 8-pin mini-DIP was considered small. Today, the thin, shrink small-outline package (TSSOP) offers the best economy for small board areas. But even smaller packages like the 5-lead SOT-23 are being put to work, delivering significant board-space savings. Last year, Microchip squeezed a 1024-bit I2C-compatible serial EEPROM into a SOT-23, which measures just 3 by about 1.5 mm (Fig. 1). The package saves 70% of the board space versus a package such as the 150-mil, 8-lead SOIC, and 50% against an 8-lead TSSOP.
Packages are growing smaller still. In a joint development announced last year, Xicor, in conjunction with ShellCase Technology, developed a chip-scale package that promises board-space requirements no larger than the area of the chip itself (perhaps 1 by 2 mm). In the next year or more, expect to pay a premium for this type of packaging. The initial manufacturing costs are high, but the package does hold the promise of lower cost once it's in volume production.
Also in the past are the times when a 5-V-compatible device would fit all system needs. A wide range of operating voltages are now used by the systems being designed. The EEPROMs must be able to operate from supply voltages as low as 1.8 V. The chips also must draw very little current—typically 1 mA or less when reading or writing data, and just a few microamps during standby.
Just about all of the serial-EEPROM suppliers have developed families of devices that are optimized for various operating-voltage ranges. Typically, they fall into 1.8 to 5.5 V, 2.5 to 5.5 V, 4.5 to 5.5 V, or some similar assortment. Even within one range, many companies create further subcategories for low and ultra-low power classifications. The designer gets a multitude of product options from which to select and optimize the final system design.
When first released over a decade ago, serial EEPROMs typically offered a simple two- or three-wire serial interface and capacities of a few hundred to a few thousand bits. Part of that limitation was due to process technology, but the serial protocol also created an artificial limit of about 16 kbits. The blame for that falls on the single-byte address that was used in the original MicroWire and I2C buses. Enhancements to the protocol extended the address capability to 2 bytes and beyond so that chips with megabit capacities can be accessed.
Currently, the basic interfaces are the same and small-capacity devices are still in great demand. But thanks to improvements in process technology, higher-capacity devices are readily available. Chips with capacities of up to 256 kbits are in mass production. Still higher-density versions, with 512-kbit and 1-Mbit capacities, are on the drawing board. They're expected to sample later this year.
The serial interfaces that tie the memories to the host system are changing to meet multiple system needs. MicroWire, the simple three-wire interface created by National Semiconductor Corp., Santa Clara, Calif., was the first of the serial buses. Its simple protocol and structure employed a serial clock line and both serial-data input and serial-data output signals. The company used MicroWire as an expansion bus on its microcontrollers. Various peripherals, such as memory or an analog-to-digital or digital-to-analog converters (ADC or DAC), could then be added very inexpensively and without requiring relatively scarce parallel-port pins. That product line is no longer offered by National Semiconductor. The products were transferred to Fairchild Semiconductor and are now part of that company's serial-EEPROM line.
At about the same time that National created MicroWire, Philips developed a chip-to-chip serial bus of its own. Requiring only two wires to handle clocking and serial-data transfers, the Inter-IC bus is what's now known as I2C. It was initially intended to move data and control information between the different chips of a multi-chip system, such as the main circuit board in a television receiver. The interface only requires a serial clock line and a bidirectional data line. The state of various bits sent to the memory in the first byte gives the device its instruction (read or write, for example). It also provides the address so that the proper location on the chip can be accessed. The next byte transferred contains the data (either read from or written to the memory).
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