Design geometries continue to shrink. Of course, this should come as no surprise to anyone now that deep-submicron (DSM) design and nanotechnology have become part of every engineer's staple diet. But just how low can design geometries go? According to a recent effort completed at the Massachusetts Institute of Technology Lincoln Laboratory, Lexington, Mass., they can reach 0.05 µm.
This development is intriguing because it was accomplished with existing optical-lithography tools. Until now, many in the industry had come to believe that optical lithography was near death—unable to extend beyond 100 nm. But the Lincoln Laboratory results not only disprove this ominous prediction, they suggest that with prudent use of phase shifting, optical lithography can be extended much further than was ever thought possible.
Lincoln Laboratory achieved these results through the use of phase-shifting software developed by Numerical Technologies Inc. (NumeriTech), San Jose, Calif. The software, used in conjunction with 248-nm optical-lithography equipment, resulted in 50-nm (0.05-µm) transistor gates on ICs. This development is thought to be the first successful fabrication of the world's smallest gate-length transistors ever patterned by direct optical lithography.
The devices were fabricated as part of a program sponsored by the Defense Advanced Research Projects Agency (DARPA). The program involved sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS.
For additional details about this development, go to the NumeriTech web site at www.numeritech.com.
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