The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips. With the IEEE-Std 1800-2005 System-Verilog standard, the industry has a complete, unified language capable of handling these challenges for today and tomorrow. The unprecedented level of vendor support, rapid adoption by hundreds of development teams worldwide, and dozens of tapeouts all attest that SystemVerilog is the right language at the right time.
More than 40 EDA, IP, and training vendors have announced more than 90 products and services supporting SystemVerilog. Project teams can adopt it today with industry support for their path to tapeout. Yet the ratification of a standard and the availability of vendor support aren't by themselves sufficient motivation for development teams to commit to SystemVerilog. The benefits users are experiencing are the main reasons for widespread adoption. In fact, SystemVerilog offers many features that make life easier for design and verification engineers.
Designers are using the language to capture their designs in one-third to one-half of the RTL code required in the past. This clearly speeds up the design process. It also accelerates verification, since fewer lines of RTL mean fewer bugs. Further, designers no longer have to choose between Verilog-2001 and VHDL. SystemVerilog has all the capabilities of these languages and more.
Verification engineers are using the testbench features of SystemVerilog to apply the most advanced verification techniques. Today's large, complex chips require constrained-random, cover-age-driven testbenches to minimize the effort of writing manual tests, maximize reuse of verification components, and accurately assess verification progress. SystemVerilog provides all the constructs necessary to build such testbenches and greatly increase the chance for first-silicon success.
Both design and verification engineers are using SystemVerilog's rich assertion capability to document design intent in executable form. SystemVerilog assertions have several unique features, including specification in the RTL design files, that foster rapid adoption throughout a project team. They work with both simulation and formal verification, maximizing their benefit to the team throughout the development process.
Another important aspect of SystemVerilog is that it can be adopted incrementally. Some users are taking advantage of its assertion and verification capabilities while continuing to design in VHDL. While teams may choose to adopt the language in stages, maximum benefits are achieved by using all of SystemVerilog's features. For example, the ability to compile and optimize the design, assertions, and testbench together can improve performance in simulation by three to five times.
SystemVerilog is also a valuable language for system-level design. It's being used for transaction-level modeling, freely inter-mixing with models written in SystemC and sharing a common verification environment. SystemVerilog defines a standard mechanism for communication with C/C++/SystemC code, allowing a single testbench environment to verify transaction-level models, RTL designs, and gate-level implementations.
Methodology is critical for system-on-a-chip success, laying out a path for adoption and specifying best practices for using any new technology. The Verification Methodology Manual for SystemVerilog, authored by industry experts, documents a comprehensive approach that spans the system-level and RTL domains. This solution is open to the industry. Library source code is available at no charge so users can apply the methodology using SystemVerilog products from multiple vendors.
SystemVerilog has ended the language wars by unifying design, assertions, and testbench support into a complete language. Designers and verification engineers can move into a new era of design and assertion expressiveness today with confidence in their results. SystemVerilog can verify system-level, RTL, and gate-level designs while laying the foundation for the next generation of design and verification innovation.
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