[Design View / Design Solution]
Save Those Watts With A Power-Aware Design Flow For SoCs
You'll lose the battle if you try to manage power as an afterthought and your latest and greatest chip's architecture is already fixed in place.
At a time when a single data center may consume more power than millions of homes1, it's easy to see that power consumption has become critically important for all designs—not just battery-powered products. Leakage power now dominates 90- and 65-nm devices, and high power consumption imposes ever more severe heat and performance penalties.
Of course, the chip-or system-level power requirements are in addition to the perennial requirements of higher performance, lower cost, and faster time-to-market. As a result, one must rethink chip design methodologies that traditionally didn't consider power reduction as a critical requirement.
Fewer and fewer designs can tolerate the traditional approach of managing power as an afterthought. Trying to correct power problems after the design's architecture is fixed makes it difficult to manage power/timing/area tradeoffs, perform functional verification, and manage the many other design steps affected by power consumption. The incremental nature of these steps results in sub-optimal power reduction. Therefore, reducing system-on-a-chip (SoC) power consumption must be considered at every aspect of the design flow—from architecture and library characterization to verification and final layout. It's also critical that the flow provides visibility and control of power/timing/area tradeoffs from the earliest stages, while ensuring continuous convergence as the design progresses.
EVOLVING TOWARD TRUE POWER-AWARE DESIGN Designing SoCs with good power management requires a design flow that integrates appropriate power-saving methodologies to the greatest possible extent. Such a flow avoids extra design hierarchy for meeting power goals. It also lets designers use the same scripts for single or multiple power domains. It eliminates unnecessary iterations. Moreover, it enables better quality of silicon (QoS).
The table provides a rough idea of the power reductions available from various techniques, along with the timing/area tradeoffs and their potential methodology impact. In general, there's a tradeoff between the amount of power reduction you can expect and the amount of work needed to apply the techniques.
The challenge for designers is choosing the most suitable power-management techniques that deliver the target QoS while minimizing the cost and risk associated with methodology changes.2 As an example, the following techniques can be added to the traditional design flow without fundamentally changing the way the tools work:
Global concurrent optimization of timing, area, and power
Leakage optimization methods, including multi-VT synthesis
Hierarchical clock gating
Low-power clock-tree synthesis
All of these techniques are useful, and the list could be even longer, including a number of other well-understood techniques that involve minimal tradeoffs for designers. Techniques such as pin swapping, operand isolation, and toggle-rate reduction may be easy to implement, but they have minimal impact on power.
Our recommendation is to certainly consider these techniques as the first step toward adopting power-aware design methodologies. Though easy to adopt, power reduction from these techniques is limited. To achieve dramatic reduction, you have to consider advanced techniques.
Two of these techniques—multiple power domains and power shut-off methods—are worth a closer look because they've become the focus for minimizing both active and leakage power in a broad range of designs. Although a number of design teams in the past used these techniques for power-critical designs, the overall methodology was manually tedious and risky. In addition, the design approach resulted in sub-optimal power, area, and timing tradeoffs. Over the last year, however, EDA tools that automate the entire design flow and permit the adoption of advanced techniques with minimal methodology impact have surfaced.
MANAGING MULTIPLE POWER DOMAINS Multiple domains can conserve power in virtually any SoC if you simply run some domains at a lower supply voltage or switch off a domain's power when it's idle (Fig. 1). Traditionally, you had to create multiple domains by partitioning the design, synthesizing each block for the lowest VDD that should support the target timing, and then put the blocks together to see whether the design worked.
This manual, labor-intensive methodology generally resulted in overpowering the voltage domains to ensure some timing margin. Today, with the right kind of tools, it's possible to use the same flow for either single or multiple domains (Fig. 2). The latter flow simply adds two steps for switch-cell insertion (to turn off each domain's power independently) and optional level-shifter/ isolation-cell insertion.
Today's multidimensional optimization lets you assign voltages to blocks without partitioning and then synthesize each block with the lowest voltage level that meets overall timing. This approach also lets you quickly perform a "what-if" analysis for voltage levels to determine the lowest voltage that can meet timing targets.
Even so, bear in mind that you need the right methodologies for physical implementation (especially for power switch-off). You must be thorough with verification. The choice of where to place the level shifters (i.e., which power domain), the size of level shifters, and the power-grid definition all can further affect design tradeoffs.
One of the basic choices that designers need to make is the number of power domains and power supplies to use. Don't be tempted to go with lots of different supply voltages to minimize power consumption, since each voltage and domain adds an area penalty.
For example, you need separate power-distribution networks for each voltage and many level shifters between domains. Also, you must supply each voltage to the chip or include voltage regulators on-chip. Of course, with the right kind of design tools, one can do early explorations to make tradeoff decisions among the number of power supplies, number of power domains, and associated area penalty.
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