Video systems operating from single +5-V supplies use ac-coupled RGB and composite video signals that operate only within the useful dynamic range of the single-supply amplifiers in the signal chain. For example, if a single +5-V supply rail-to-rail amplifier has a useful dynamic range of down to a few millivolts of ground and up a few millivolts of +5 V, the incoming video signal plus sync must be constrained to that voltage range.
Because the NTSC standard composite video including negative sync has a voltage range from -0.3 V to +0.7 V, it must be ac-coupled to the amplifier's input. Then it's level-shifted so that the 1-V p-p video signal is constrained within the amplifier's useful dynamic range. In a 75Ω, back-terminated cable driving application, the peak-to-peak voltage output swing required at the output doubles to 2 V p-p. This requires the accoupled amplifier to operate at a gain of 2 to compensate for the -6-dB cable termination loss.
In addition, a dc-restore circuit at the end of the video signal path is needed to reestablish the correct black level. Single-supply dc-restore circuits are well-suited for video systems that use separate paths for H and V sync signals. But they can't handle composite video and sync due to their inability to supply the negative sync voltage.
The Figure 1 circuit uses a single-supply, dc-restore video amplifier in a dc-restore application. The application supplies a negative output swing capability at a level sufficient to pass the negative sync signal along with the composite video. This is accomplished using a negative voltage source, plus a voltage divider (R1, R2) connected between the video amp's video output and the negative source. With the proper values of R1 and R2, the negative sync pulse can be restored, and a 75Ω back termination can be realized in this cable-driving application.
The ISL4089 DC Restore Video Amplifier is an example of a device that uses a horizontal sync logic-level signal to cycle between dc-restore and video-amplifier modes. In the dc-restore mode, a logic "0" closes the dc nulling circuit during the negative H-sync period and forces the amplifier output voltage to be equal to the voltage at VREF. When the HOLD input is set to a logic "1," the switch is opened, and the ISL4089 becomes a video amplifier with the dc correction voltage at the +IN pin stored on capacitor CX.
If CX is made sufficiently large, and the HOLD-mode correcting voltage is refreshed at each H-sync interval, droop in the dc correcting voltage is minimal and the dc reference becomes stable. The ISL4089 output amplifier can swing to within 10 mV of ground, and the composite video signal at the output will be dc-restored to the VREF level plus an internally generated 25-mV positive voltage offset.
The timing relationship between the HOLD "0" timing and the composite video input determines whether the output video contains the negative sync or not. Generating the HOLD "0" level within the negative H-sync period forces the video-amp output to 0 V at the same time that the video input is at its most negative value. Therefore, the negative sync tip voltage (-0.3 V) appearing at the output is level-shifted up to +25 mV, and the remaining positive video voltage is constrained within the amplifier's useful dynamic range.
To add the negative dc offset needed to restore the -0.3-V sync tip level, add resistors R1 and R2 to form a voltage divider from the amplifier output to a negative voltage rail (VREF). VOC is the output voltage appearing at the junction of R1 and R2 without load ZL connected, and VOUT is the amplifier output voltage.
The voltage (VOC) appearing at the junction of R1 and R2 is a function of the amplifier output (VOUT) and the external reference voltage (VREF). It can be expressed by:
VOC = (VREF-VOUT) X {R1/(R1+R2)} (1)
The Thevenin equivalent circuit for Equation 1 is shown in Figure 2. It contains a voltage source of voltage VOC in series with a resistor whose value is the parallel combination of R1 and R2. VOC is the open circuit voltage. It's equal to 2 X VL when load ZL is connected and the parallel combination of R1 and R2 is set to ZL.
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