[Engineering Feature]
Back To Nature For Next-Gen Semis
While the fight to scale down rages on, semiconductor manufacturers look more to nature for new technologies.
The semiconductor manufacturing community faces a plethora of challenges in the drive to keep Moore's Law alive and kicking (these we'll discuss later). Most IC technologies, such as microprocessors, memories, and logic devices, employ complementary metal-oxide semiconductor (CMOS) technology, which has been around since 1963. As Gordon Moore predicted back in 1965 (with a few revisions since then), the number of semiconductor components (transistors) has doubled roughly every 18 months. This often misquoted and over-quoted prediction became known as "Moore's Law."
We now live in an era where functional requirements, such as mixed-signal RF designs for wireless applications, passive components, and biological functions such as medical delivery systems, are not scaling according to Moore's Law and non-CMOS solutions are used instead.1 But as more technologies merge into system-in-package (SiP) solutions, the integration of CMOS with other technologies, as well as new packaging technologies, will become increasingly important.
Current technology research extends from electron-beam lithography and low-k gate dielectrics to using nature's structures to revitalize Moore's Law and, perhaps, make a quantum leap (literally) ahead.
Today, most large semiconductor manufacturers offer or use 65-nm process technology, with feature sizes as small as 35 nm. To put this number in perspective, it's about 2000 times smaller than the diameter of a human hair. To think we are only two orders of magnitude away from building features at the atomic level (around 100 pm, depending on the element) is mind-boggling.
But can we build features at the atomic scale? It's already being done to a degree in a memory technology named spintronics (Fig. 1). Here, semiconductor manufacturers are researching the use of the quantum spin of electrons and their charge state to indicate a stored memory bit.
In the remainder of this article, we'll explore semiconductor manufacturing issues and trends, plus logic and memory technologies, that will take us out to the year 2020 and beyond.
CURRENT TRENDS There is a grandiose number of major issues1 facing semiconductor manufacturers over the next several years:
Scaling CMOS to 32 nm and below: High channel doping will be required; thus, designers must find ways to reduce gate-induced drain-leakage (GIDL) current and threshold voltages variations while scaling the supply voltage.
Signal isolation in RF, analog, and mixed-signal design for wireless: As devices scale down while integration increases, signal isolation between the digital and analog portions of the chip becomes a daunting challenge. Also, wireless devices built for low-standby-current applications require high-K gate dielectric materials and metal gate electrodes, which complicates predicting threshold and current mismatches along with pink noise. Increased integration will also challenge the way we think about testing, putting pressure on enhancing mixedsignal co-design and co-verification.
Lithography (the method of producing patterns on a wafer substrate): Immersion lithography uses ultra-pure water to replace the air gap between the final projection lenses and the wafer. It also increases the resolution of the pattern etching process. Immersion lithography, along with more refractive lenses, will be needed for 32-nm process technology. 32 nm will be the approximate limit that can be reached using a 193-nm wavelength laser. Breaching the 193-nm wavelength limit used in optical lithography requires a new technology. So far, those entering the fray include extreme ultraviolet lithography (EUVL), maskless lithography, and imprint technology, with EUVL being the likely candidate to take us down to 16 nm and below.
Interconnect: As feature sizes shrink, signal propagation delay and power consumption must be minimized using a low dielectric constant (low-K) material of around 2.0. The challenge after that will be to make a non-brittle, porous dielectric to reduce the dielectric constant to around 1.4 or less.
450-mm wafers: The move to 450-mm wafers (from 300 mm) will roughly double the number of dies per wafer. Expectations for this technology's arrival are around the year 2012. If this date is to be met, though, the industry must significantly step up research efforts and adopt numerous standards in the areas of wafers, metrology, and processing equipment.
On-chip parallelism: Servers and even personal computers have taken advantage of parallel processors for years. We've also seen increases in onchip parallelism over the years, with such things as pipelining, math coprocessors, and multithreading. Today, though, true independently operating multicores are all the rage, but they do provide their own set of challenges.
According to Intel CTO and Senior Fellow Justin Rattner, when multiple independent cores and multithreading are combined, we lack the quantitative tools to deal with sophisticated scalable on-die fabrics and must provide better explicit thread support. These issues will be overcome using architecturealgorithm co-design with new instructions and cache design improvements.
Design For Manufacturing (DFM): Designers will need to pay increasing attention to DFM (See "10 Semiconductor Manufacturing DFM Rules Every Designer Should Follow," p. 47).
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