With signal speeds on the rise in a wide range of applications, maintaining signal integrity (SI) and minimizing the effects of EMI have become growing challenges in countless board-level designs. Clock rates of several hundred megahertz have become commonplace, and in some applications, logic devices are breaking the 1-GHz barrier. Naturally, as on-chip signal speeds get faster, bus speeds escalate as well.
Consider also that component and I/O densities on the pc board are rising, too. The combination of faster signals and tighter line spacings means high-speed effects are becoming more serious. Nowhere are these effects more critical than at the connector. Board-level interconnects for high-speed systems require consideration of such factors as crosstalk, ground bounce, propagation delay, skew, impedance, return loss, and attenuation.
The relative importance of each of these parameters depends greatly on the application. Furthermore, these electrical characteristics tend to vary nonlinearly as frequency increases. SI issues, which are present to some degree for signals even as slow as a few megahertz, become especially troublesome as frequencies creep into the gigahertz range. More significant than the actual clock speed is the edge rate of the signal. If the round-trip transit time for a signal over a given path is greater than the signal's edge rate, then that path must be treated as a transmission line, and the designer must consider SI effects.
As a result, even designs with relatively slow clock speeds may suffer unwanted high-speed effects. The problem might occur when a logic device found in an existing design is replaced—perhaps because of obsolescence or the need for a smaller package—with a newer version that has a higher edge rate. Nevertheless, the focus on developing high-speed connectors reflects the steady ramping up of clock speeds. As John Hynes, a new-products development manager at Samtec in New Albany, Ind., observes, "The push is to get to 1 GHz cleanly."
Of course, the definition of "clean" performance is anything but. It varies from design to design and depends largely on how the connector is applied in the application. The choice of differential over single-ended signaling becomes a must at higher frequencies. The ground structure—both the ratio of signal to ground pins and their configuration—markedly affects results, particularly for connectors without a built-in ground plane. Board design also is critical. Layer-to-layer stackup, goldfingers, and vias all have an effect on connector performance. Recognizing this fact, connector vendors are providing customers with reference layouts as well as design guidelines for their components.
Cost-Performance Tradeoff
Getting board-level connectors to operate at a gigahertz or more isn't just about building high-speed connectors. It's about achieving the necessary performance versus cost. Connectors such as the BNC and SMA types designed for microwave work can more than satisfy many of the electrical performance requirements of high-speed systems. But their pricing is orders of magnitude above that of traditional digital pc-board interconnect components. And, they don't offer the required high density of signal contacts.
Existing board-level interconnect products are steadily improving, as evidenced by some of the recently introduced backplane and board-stacking devices described below. Simple techniques, like surface-mount board attachment or the insertion of a ground plane between rows, help.
In the future, development of materials with improved dielectric constants, novel shielding configurations, and different types of metals will likely improve high-frequency performance. As the skin effect becomes the main path for conduction at higher-frequencies, contact-pin plating will matter for its effect on resistance as well as for its ability to fight corrosion.
Unfortunately, semiconductor development seems to be outstripping connector development. While Intel may be introducing chips that run at 1.5 GHz and chip designers craft even faster ICs in the laboratory, most interconnects aren't close to handling these types of signals. Max Peel, president of Contech Research—a company that specializes in connector testing in Attleboro, Mass.—has observed this discrepancy first hand. When performing a full SI characterization on a board-level connector, the company runs its tests just up to a frequency of 1 GHz because, as Peel says, "the connectors generally cannot go beyond that."
Because of the relationship between a signal's edge rate and transit time, one aspect of high-speed connector development is minimizing the length of the signal path through the connector. Doing so can reduce the effects of connector parasitics while keeping the signal within the controlled-impedance environment of the board longer.
However, reducing the length of signal-contact paths isn't the greatest challenge for connector developers. Michael Munroe, a strategic product marketing manager at ERNI Components Inc., based in Chester, Va., notes that pc boards and connectors are both capable of carrying faster signals than they are currently required to handle. According to Munroe, "The most challenging bottleneck is the interface between the connector and the board. Every solution must be a compromise between density, performance, and routeability. The typical close grid of 0.5- to 0.8-mm vias used to support through-hole high-density connectors will become the future technology focus."
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