[Design View / Design Solution]
Digital Current-Mode Control Challenges Analog Counterparts
Switch-mode power supplies can use digital current-mode techniques for protection against peak currents, magnetic field "ratcheting," and input-voltage variations.
Digital control of switch-mode power supplies (SMPSs) is becoming practical thanks to the evolution of low-cost, high-performance devices with peripherals designed for power-conversion applications. Also, current-mode control is challenging voltage-mode techniques for SMPS digital designs. Combining digital control with current-mode topologies can bring higher performance than combinations of analog or voltage-mode approaches.
Early SMPS designs used voltage-mode control. A ramp generator drives one input of a voltage comparator, and the error signal from the error amplifier/loop filter drives the other input (Fig. 1). The result is a pulse-width-modulation (PWM) pulse based on the voltage error signal. This circuit had two basic limitations, though. There's no inherent current limiting to protect circuit components, and it responds slowly to input and output transients.
As SMPS designs matured, designers moved to current-mode control (Fig. 2). Here, a current-feedback signal driven by the inductor current replaces the ramp generator. The result is a system in which the error signal directly controls the peak current in the inductor, eliminating potential circuit failures due to excessive current conditions. Because current-mode control manages the inductor current, the pole or delay due to the inductor is effectively removed from the control loop, improving the system's transient response.
GET THE AVERAGE An important issue with most analog current-mode PWM controllers is that they can only measure peak current. Designers really need the ability to measure average current, because the average current is integrated with the output capacitor to produce the desired output voltage.
Usually, designers can approximate the average current as half the peak current. For duty cycles less than 50%, there's enough time for the inductor current to decay to zero before the start of the next PWM cycle. As long as the inductor current reaches zero by the end of the PWM cycle, the average current will equal half the peak inductor current (Fig. 3).
This design generally works well. But when the duty cycle is greater than 50%, some issues arise. Primarily, the average current is no longer approximately equal to half the peak current (Fig. 4). As the PWM duty cycle rises above 50%, the average current becomes increasingly larger than what's expected by measuring peak current.
The resultant output voltage will be higher than desired, and it will continue to rise until the slower voltage-control loop readjusts the current set point. The output voltage will then drop below the desired level. This process, known as subcycle oscillation, will repeat.
To fix this current-mode instability, analog current-mode controllers employ slope compensation that adds a falling-edge sawtooth voltage to the current threshold generated by the voltage-error amplifier (Fig. 5). This creates a new current threshold for the current-limit comparator, which more closely tracks the average inductor current.
DIGITAL CURRENT-MODE CONTROL A digital approach to current-mode control overcomes many of the limitations of digital voltage-mode PWM controllers. Digital current-mode control protects transistors against peak currents, eliminates magnetic-field "ratcheting" in the magnetic components, rejects input-voltage variations, and simplifies control-loop compensation.
Current-mode control also uses the error voltage to control the maximum inductor current, which turns the inductor into a voltage-controlled current source. As a current source, the inductor no longer generates a pole in the loop's frequency response. This changes the loop from unconditionally unstable to conditionally stable, simplifying loop-filter design.
Digital signal controllers (DSCs) can perform digital current-mode control with the proper on-chip peripherals. However, many lack analog comparators and analog-to-digital converters (ADCs) able to measure inductor current at the appropriate points during the PWM cycle. Without some means to accurately measure current at the desired point, the DSC would have to constantly measure the inductor current with the ADC during the PWM cycle to "catch the moment" when the inductor current reaches the desired level.
Achieving 12-bit resolution demands up to 2048 ADC current conversions per PWM pulse. The required ADC sample rate would be 1 billion samples/s. In addition, sufficient processing power is needed to collect these 1 billion conversions, compare each to the error signal, and shut down the PWM output when reaching the desired current. Conservatively, this means designers need a processor capable of a billion instructions per second (BIPS). As such, it's not cost-effective.
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