Digital Brings More Memory, Gates, Speed The ability to process data in the digital domain has opened many new opportunities and application areas. Starting with diode-transistor logic (DTL) circuits in the '50s, to the first IC in 1959, to the first 4- and 8-bit processors in the early '70s, and to today's 64-bit and very-long-instruction-word (VLIW) CPUs and gigabit memories, digital technology has become the stuff that designers build dreams on. Making much of this possible is the relentless drive to shrink transistor dimensions and metal line widths while reducing the operating voltage. This combination will let chips pack more transistors, run at multigigahertz rates, and consume less power.
If we could divide the growth of digital technology over the last five decades, we would see that the '50s were the discrete era, the '60s were the era of commodity logic, and the '70s the era of gate arrays. The '80s were the custom design era and the '90s were the era of programmable logic and system-on-chip (SoC) design. The current decade promises to be the full-fledged era of SoC design.
During the '60s and early '70s, huge catalogs of standard DTL and TTL parts dotted many engineers'desktops. But the blizzard of logic-device introductions made it hard to keep the right parts in stock. So in the early '70s, two new directions took shape—one to user-programmable logic and another to mask-programmable gate arrays and ASICs. The early '70s also saw the birth of the microprocessor, the DRAM, the UV EPROM, and the single-chip microcontroller unit (MCU). These four devices changed system design. A microprocessor, some memory, and some software could execute the logic algorithms and replace boards of logic chips. Of course, additional function-specific logic functions were required to complete the system.
As designers packed more transistors on-chip, processor complexity, memory density, and logic capabilities all started to skyrocket. Gate arrays grew from a few hundred gates to megagates by the early '90s. Processors grew from 8- to 16- to 32- to 64-bit word sizes. DRAMs exploded from 1 kbit/chip to over 16 Mbits/chip by the early '90s and to 1 Gbit/chip today.
In the realm of nonvolatile memory, UV EPROMs survived through the early '90s but faded as electrically reprogrammable flash memories became a more cost-effective and higher-performance solution. Today, flash technology can be used to fabricate standalone memories that hit densities of up to 1 Gbit/chip. Along with this explosion of density and performance gains, new general-purpose but targeted functions like digital-signal processors, graphics controllers, DRAM controllers, PC chip sets, and many others were created to support the new high-growth industries, especially in personal computing and communications.
By the early '90s, the ability to integrate full SoCs while drawing upon intellectual property libraries of predesigned functions opened up additional opportunities in the ASIC world for custom solutions. The ability to integrate millions of gates on a chip has made products that were once revolutionary now commonplace—cell phones, PDAs, laptop PCs, digital cameras, and a lot more. Today, it's not unusual to design a chip with 5 million gates and 100 million transistors, assuming there's lots of on-chip memory. Over the next two years, 10 million- to 15 million-gate chips will be possible.
Future systems will continue to leverage advances in integration. As process feature dimensions drop to 0.1 µm and below over the next year or two, chip gate counts will continue to escalate. Furthermore, advanced processes that employ eight or more layers of low-resistance copper interconnections and silicon-on-insulator structures to reduce leakage and parasitic capacitances will considerably enhance circuit performance.
These advances will permit SoC designs to incorporate multiple Pentium- or PowerPC-class CPUs on-chip along with megabytes of cache memory. Designers will also be able to craft highly parallel processors with hundreds of compute engines on one chip. To support these high-performance processors, DRAM capacities and performance will increase. We can expect 1-Gbit SDRAMs employing the new second-generation double-data-rate (DDR2) interface with data-transfer rates of 600 to 800 Mtransfers/pin. Future flash memories will offer 2- to 4-Gbit capabilities, and newer memory technologies, such as the ferroelectric RAM (FRAM), will go mainstream with 16-Mbit densities.
More specialized circuits such as DSPs will also benefit from highly parallel architectures, including the use of VLIW architectures, to achieve throughputs of well over 50 billion operations/s. There's no end in sight to the advances that digital technology will permit. Twenty-five years ago, the PC as a concept was barely feasible. Today it's an essential tool. In another 25 years, who knows what the next "big" product to drive the market will be? It's entirely up to your imagination.
Water stacking will go into commercial memory production by a newcomer to the memory market, Tachyon Semiconductor (www.tachyonsemi.com), which will leverage the stacking technology to create multiple layers of memory cells over a base layer of control circuits, creating high-performance, high-density memory chips.
Samples of the DDR2 SDRAMs will be released by several companies. The improved interface on the DDR2 SDRAMs will reduce system overheads and deliver data faster. The DDR2 interface will also offer better immunity from noise than first-generation DDR memories.
1-Gbit DRAMs will enter volume production. The relentless need for larger and larger memory spaces in personal computers, servers, and other equipment continues to turn the crank on memory density. 1-Gbit DDR SDRAMs will be sampled by Samsung (www.samsungsemi.com), Infineon Corp. (www.infineon.com), and other companies in 2002.
The continued reductions in feature size will allow designers at Samsung, Toshiba (www.toshiba.com), and other companies to implement flash memories with densities of 1-Gbit/chip using a single-bit/cell approach in 2002 and 2 Gbits/chip using multilevel charge-storage schemes.
Novel one-time-programmable technology using layers of polysilicon diodes will debut in very-low-cost digital film memories developed by Matrix Semiconductor (www.matrixsemi.com). The memory arrays' low cost will let the memory cards be sold at prices competitive with rolls of film. Therefore, they're well-suited for cost-sensitive, one-time-use applications.
Enhancements to the nonvolatile version of the multilevel charge-storage scheme will allow up to 4 bits/cell. That will double the storage capacity of today's dual-bit per cell schemes without doubling the chip area.
Next-generation Rambus RDRAMs will be sampled in 2002. They'll have a simplified internal multibank architecture to reduce cost and power and improve performance. The simplified architecture will allow the RDRAMs to more directly compete with SDRAMs on a price/bit basis.
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