FPGAs need flexibility, which in the past related directly to the types of designs a given FPGA could implement. Wouldn't it be nice to have more control over power consumption in addition to design flexibility? Altera s Stratix III delivers that with its Programmable Power Technology (PPT). PPT maximizes the performance of high-speed paths while minimizing power usage elsewhere. Each logic, DSP, and memory block is analyzed to determine if it should be placed in high-speed or low-power mode. PPT is possible thanks to PowerPlay, a feature of Quartus II that automatically analyzes the design to determine critical path signals that demand high performance (see the figure). The decision to place a block in high-speed or low-power mode is based on timing constraints and the clock slack at that block.
Stratix III also provides the ability to set the core operating voltage to 1.1 V or 0.9 V. Choose 1.1 V for applications that need higher performance and 0.9 V for applications that need minimal power consumption. Altera is the only company currently offering PPT and a settable core voltage. Furthermore, the Stratix III provides a very simple gateway to Altera s HardCopy structured ASICs, which are low-cost, functionally equivalent, and pin-compatible with Stratix III.
Compared to Stratix II, Stratix III devices are 25% faster and twice as dense. Stratix III also supports a 256-bit AES security key, which will help keep the device safe from being copied, reverse engineered, or otherwise compromised.
When it comes to signal integrity, Stratix III FPGAs offer a high power and ground pin to user I/O pin ratio, along with optimized signal return paths, adjustable slew rates, staggered output delays, and calibrated on-chip terminations. These features will help reduce potential issues with simultaneously switching output noise (SSO or SSN). Pricing will start at $549 for the EP3SL150 in 1000-unit lots.
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