Middle age takes its toll, be it animate or inanimate. The "application-specific" industry, regarding both ICs and standard products, is no exception. Don't expect any sporty red convertibles, though.
Tough times await as customers expect better performance for the same prices. ASICs will need to change their ways to survive, with designers taking preventative measures in the form of up-front designfor-manufacturing (DFM) rules.
Meanwhile, analysts are calling for new value propositions. The industry also needs to learn to play well with others in the form of mergers, alliances, and collaborative efforts. The costs of foundries continue to rise. And, developers need to refine and find new materials to keep the process shrink alive. The fallout of all these factors will be cost-cutting measures, ultimately leading to layoffs.
Value Propositions Must Change Research firm Gartner believes the ASIC/ASSP industry needs to change its value proposition or face the consequences. That's because margins and design opportunities are shrinking while the industry consolidates its resources.
Take the DVD market. The average selling price of DVD recorders has dropped from about $525 in 2002 to around $125 now, and it will continue to fall to the $50 mark by 2010. Yet design costs have soared from a few million dollars to over $10 million today and are expected to reach over $30 million by 2010.
The non-recurring expenses (NRE) for ASIC/ASSP designs drive up costs as process technology shrinks to 65 nm now and 45 nm soon. Meanwhile, customers demand more features as companies attempt to penetrate more global markets with the same product.
In other words, DVDs now must handle several types of audio and video codecs (with more on the way), such as MP3 and MPEG2. And to work in different countries, DVD recorders must handle several video standards, including NTSC and PAL. It's becoming such a challenge to be profitable in the DVD market that well-known manufacturer Lite-On will stop selling its DVD recorders worldwide because it's seeing too many returned products.
In addition, more features are being integrated into a single chip. With rising design costs, ASSP design starts will continue to decline, dropping from over 6000 in 2000 to about 4000 in 2010.
DFM Or Bust So, things are changing. For instance, ASIC and ASSP designers now need to consider DFM rules. But how much DFM do they really need to consider?
"One-hundred percent of the responsibility for DFM falls on the designer, because it is the designer who is ultimately responsible for selection of all the elements, from tools to foundry, in the design chain," says Chuck Byers, director of brand management for TSMC. "It is up to the designer to understand the substance of any DFM architecture and to act accordingly to ensure the time-to-ramp, time-to volume, and time-to-money of the design."
ASIC/ASSP designers are trained to understand electronic circuits and the hardware description language required to implement their design. They're also expected to know how to deal with thermal issues and new materials, thanks to the European Union's Restrictions on Hazardous Substances (RoHS) initiative. Going forward, engineers will be expected to know more about manufacturing than ever before.
But being DFM-aware isn't enough. Engineering flows should be revamped to revolve around DFM. TSMC suggests a reference flow in which DFM constraints are employed consistently throughout the design flow, including the cases where external IP is used. Of course, designers must be particularly careful with internal IP reuse. They can't assume a given IP block that once worked with an older process technology will work with the new one.
Once designers determine a reference flow, it's best for them to review that flow with their foundry, IP vendors, packaging vendors, and EDA vendors to ensure everyone is on the same page. In essence, designers are creating a tightly coupled ecosystem that heavily involves their design partners and considers DFM throughout the design process (see the figure).
TSMC took the idea of a DFM-aware ecosystem to the next level by designing a unified data format in the form of a database to help members of the ecosystem ensure DFM compliance at 65 nm. TSMC developed the database format to align lithography process check (LPC), chemical-mechanical-polishing (CMP) analysis, and critical area analysis (CAA) to TSMC's manufacturing data format. This will ultimately empower ASIC and ASSP designers to manage DFM rules in one area, irrespective of the tool or vendor.
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