Instruments such as those in LeCroy's Serial Data Analyzer (SDA) family measure jitter and create eye patterns based on the time difference between crossing points in the data stream and those of an ideal reference clock. This involves sampling at a high rate and processing a long record.
Specifically, all of today's high-speed serial data standards require minimum sampling rates of 20 Gsamples/s and rise-time capabilities faster than 300 ps. Setting the phase-locked loop requires a minimum of 3000 data edges. So for a signal consisting of 12 samples per bit, you would need a minimum of 50 ksamples. LeCroy says that 400 ksamples is the minimum practical record size to produce acceptable results.
It's best to use a clock recovered from the data. LeCroy's SDAs use a feedback control loop that corrects each period of the clock by adding a portion of the error between the recovered clock edge and the nearest data edge in a single-pole, infinite-impulse-response (IIR) low-pass filter.
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