[Technology Report]
FPGA Design Issues 201
You may be familiar with the basics. But to resolve the challenges that plague today's FPGAs, you need to sign up for the next-level course.
It doesn't matter if you're the logic designer, hardware engineer, or systems engineer, or if you wear all of those hats. If you use an FPGA in any sort of complex system with high speeds and multiple protocols, you'll likely wrestle with device configuration, power management, intellectual property (IP), signal integrity, and other key issues. But you needn't face these challenges alone. Applications engineers at the top FPGA houses face them every day, and they've come up with some guidelines and solutions that will make your job easier.
I/O SIGNAL ASSIGNMENT ORDERING FPGAs that offer the most multifunction pins, I/O standards, termination schemes, and differential pairs have the most complicated guidelines for assigning signals (see "For The Best FPGA Advice, Ask The Experts,"). While Altera has no guidelines, as its devices are simpler to implement, Xilinx's guidelines are pretty complex. In any case, there are some common steps to keep in mind when assigning signals to I/O pins:
Use a spreadsheet to list all planned signal assignments, along with their important attributes like I/O standard, voltage, required termination scheme, and associated clocks.
Review the manufacturer's bank/region compatibility rules.
Consider using a second spreadsheet to map out the FPGA to determine which of the pins are general-purpose versus specialized, which support differential pairs and global and local clocks, and which are required for voltage references.
Using the information in the two spreadsheets and the bank compatibility rules, assign signals to pins from most constrained to least. For example, you may need to start with serial buses and clocks that typically may only be assigned to specific pins.
Assign signal buses again from most constrained to least. Considerations like simultaneously switching output (SSO) issues and incompatible I/O standards may need to be carefully weighed during this step, especially if you have a considerable number of high-speed outputs or use several different I/O standards. If your design requires local/regional clocking, you'll likely need to use pins in the vicinity of your high-speed bus, so keep that in mind as well. If the selected I/O standard for a given bank requires voltage-reference signals, remember to keep those pins free. Always assign differential signals before single-ended ones. And if on-chip termination is provided, other compatibility rules may apply.
Assign remaining signals where appropriate.
During this process, consider writing an HDL file that contains only the port assignments. Then, add the necessary supporting information for the I/O standard and so on by creating a constraint file using the vendor-provided tool or by manually using a text editor. With these basic files in place, you can run the place-and-route tool to see if you've overlooked some rule or made an incorrect assignment (Fig. 1).
This will let you start working with the layout engineer and planning for pc-board (PCB) routability, escape planning, thermal issues, and signal integrity early in the design process. The FPGA tools may be able to assist in these areas and help resolve issues, so be sure you understand the capability of your toolset.
The longer you wait to consult a layout expert, the more likely you will deal with complex issues and iterations that were probably avoidable with some up-front analysis. Once you're satisfied with the signal assignments, lock them down using the constraint file.
SIGNAL INTEGRITY Most advanced FPGAs can handle parallel bus speeds of hundreds of megahertz and have serial interfaces that operate in the gigahertz range. At these speeds, you need to understand the basics of signal integrity, because dealing with high-frequency (short rise/fall time) signals brings a torrent of analog issues into our nice and neat digital world.
Set aside some time for reading the literature from FPGA vendors. Even if you have a specific device or vendor in mind, read literature from other vendors, too, since they tend to view the outside world differently. You will note the different viewpoints on what makes a signal high speed, how much delay can exist between switching signals and still consider them simultaneous, and so on. The FPGA vendor tools are usually quite capable of performing some basic signal-integrity analysis, so be sure you fully understand a given tool suite's potential.
Also, there are hundreds of books on signal integrity and noise reduction. If you're a novice or need a refresher course, consider Signal Integrity Issues and Printed Circuit Board Design by Douglas Brooks. For a more in-depth discussion, try High-Speed Digital Design by Howard Johnson.
FPGAs may wreak havoc on signals in a system (or other FPGA signals) with too many high-speed SSOs, which cause noise known as simultaneous switching noise (SSN). Also called ground bounce or VCC bounce, for single-ended standards, SSN is caused by multiple output drivers simultaneously switching and inducing a change in device voltage with respect to system voltage as the outputs source transient current for low-to-high transitions and sink current during high-to-low transitions.
The low-to-high transition causes VCC to sag while the high-to-low transition causes ground bounce. Since capacitance normally is built in between the VCC and ground planes, SSN is typically seen on both references. Ground bounce on a low-to-high transition, then, is likely.
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