Consumer markets continually demand cheaper, easier-to-use, and more portable applications. Add to that manufacturing technology trends and these demands have pushed the semiconductor industry to higher levels of integration. Just consider digital applications that combine data processing –– games, voice, music, and video –– with memory, encryption, and copyright-protection capabilities on single silicon chips or systems on a chip (SoCs) with hundreds of millions of gates. Indeed, this is quite an achievement that required significant innovations in EDA software.
Nonetheless, there is a greater challenge yet to be addressed that would allow huge digital devices to communicate wirelessly. Consumers of electronics products continue to struggle with the invasion of cables, which are required to connect their televisions with a video camera or a computer, Internet, or cell phones. Ideally, most consumer-market devices would feature wireless communication, since the proper cable always seems to be unavailable, or too short, or broken. Typically, wireless communication is implemented with separate die, which ostensibly carries consequences in the form of larger devices with shorter battery life and notoriously higher cost.
But actually, the part about higher cost is not true. That’s because the integration of radio-frequency (RF) blocks –– a necessity for wireless communication –– on the same die with digital processing causes a time-to-mass-production incompatibility with product life cycle as well as dramatic yield drop.
Of course, yields tend to decrease when integrating two die into one, but falling yields for devices that combine digital with RF are caused by design errors and electrical signal-integrity (ESI) issues. ESI increasingly represents a challenge for all designers because it lengthens design cycles and forces extra prototype manufacturing.
The growing demand for low-cost consumer wireless applications requires unprecedented levels of integration. Huge digital intellectual-property (IP) cores, such as microprocessors, signal processors, and encryption engines, are being assembled together with analog functions (e.g., power-supply control, data conversion) and with RF blocks. Unfortunately, in ESI terms, those analog blocks can act as aggressors, generating noise that’s disseminated through the entire system to ultimately degrade the operation of the sensitive (victim) RF circuitry.
Furthermore, this complex ESI mechanism affects digital circuits through IR drop, crosstalk, and delay, as well as analog and RF. The impact on RF is even more complicated, because even a low noise level can produce dramatic influences at any time, and not just in proximity to specific signal transitions, which is often the case in the digital domain.
In the past, detection of failures related to noise interference in mixed digital/analog/RF systems fell to the analysis of painstaking measurements; thus, finding and correcting them was uncertain at best. Even the availability of early noise estimation cannot always prevent iterations from final layout back to functional redesign. Because functional simulators lack actual descriptions of system noise reaching victim blocks, respins occur over lengthy and tedious functional and physical implementation loops.
The solution is to automate the feedback of noise figures computed during ESI analysis within RF simulators, making it possible to assess the victim blocks’ immunity, or lack thereof, to real-world system noise. Existing circuit design techniques can now be applied more effectively during function implementation to reach the best possible noise margin. As a result, the physical implementation loop has a greater chance for successful ESI analysis. This solution, expected by designers for a long time, is fast becoming a must-have requirement to meet consumer demands for portable applications.
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