With a new breed of analog/mixed-signal foundries arriving on the scene, fabless and fab-lite companies can create a huge variety of high-yielding designs. As a result, these fabless and fab-lite companies are able to successfully compete with the IDMs in the analog/mixed-signal market. These companies offer something different than traditional CMOS foundries with analog libraries, and it's useful to understand the difference.
Pure-play CMOS foundries have much to offer. Increasing chip density makes it possible to transfer more analog functions into the digital domain. Analog signals are digitized as soon as possible, processed by a digital platform before the data is reconverted to analog output values at the very end of the process.
But that's an oversimplification. There's a need for mixed-signal ICs that encompass digital, analog, high-voltage (HV), radio-frequency (RF), and nonvolatile-memory (NVM) technologies—in many cases, all on the same piece of silicon. Convergence of these different technology platforms can pose serious challenges (Fig. 1).
One such challenge is environmental. Often, analog/mixed-signal devices are required to work in a harsh, unfriendly environment, where they must cope with high temperature differences, high voltages, switching noise, or interference from neighboring elements (Table 1). Analog circuits also are much more sensitive than digital circuits, leaving performance particularly vulnerable.
Mixing technologies creates other challenges. Although the digital world essentially relies on NMOS and PMOS transistors, analog/mixed-signal designs incorporate both CMOS and bipolar junction transistors (BJTs). Another key difference is the presence of a large variety of passive elements, e.g. capacitors, resistors, inductors, varactors, and diodes, which have a major impact on the design's performance. As a result, the ability to accurately construct and model such passives represents a key enabler for new circuits and products (Table 2).
From a process technology perspective, combining a variety of active and passive elements is difficult due to conflicting optimization strategies. Many analog features require their own specific architecture unique modifications of the baseline manufacturing process flow.
More often than not, the necessary additional process steps tend to perturb existing ones due to their different requirements with respect to thermal budget or process sequence. While adhering as closely as possible to the cost-effective bulk CMOS baseline process flow, the challenge is to introduce high-performance HV transistors, passive elements, and NVM blocks without compromising the existing process steps or the cost structure in the foundry environment (Table 3).
Process Technology Analog foundries deal with these challenges with their own approaches to a modular solution. To understand how these work, it's useful to understand how mixed-signal process technologies differ from plain-vanilla CMOS. The architecture of an analog/mixed-signal process is defined by four major issues:
the passive device architecture
the active device architecture, driven by the breakdown voltage and on-resistance (RON) trade-off
the geometry, determined by the amount of logic and memory to implement
the choice of isolation technique, which is motivated by the requirement to isolate different voltage domains of building blocks and/or chip areas.
High-voltage capability is a special flavor of mixed-signal designs. Apart from the native inner voltage for data processing, which depends on the baseline CMOS technology node—1.8 V for 0.18 µm, 3.3 V for 0.35 µm, or 5 V for processes of 0.6 µm and above—mixed-signal devices may have to cope with higher input or output voltages. Typically, 5 V is needed for analog applications, and voltages above 5 V up to 120 V are required for many applications, such as those in the automotive or industrial domain. As major elements of mixed-signal circuits, HV transistors occupy between 30% and 50% of the overall chip area.
Implementing HV transistors requires fundamental technology choices that affect the cost/performance tradeoff of the design. Available options include lateral or vertical architectures, with junction, trench, or buried layer isolation, using silicon-on-insulator (SOI) technology or a bulk CMOS substrate. High-performance HV devices with optimized, low on-resistance (RON) can be realized in any of these device architectures. Due to the higher complexity of the architectures, the cost/performance tradeoff for vertical devices, buried layer technologies, or deep trench isolation SOI technologies is often skewed toward performance (Table 4 and Fig. 2).
The HV technology choice also depends on the required voltages. For HV transistors operating above approximately 40 V, SOI technologies seem to provide the most promising approach. In contrast, bulk CMOS technology offers the best cost—performance trade-off available today for high-performance transistors below 40 V (Fig. 3).
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