[Technology Report]
Backplane Switch-Fabric ICs Go To The Next Level
Next-generation switches and routers are designing in nonproprietary chip sets that support 2.5- and 10-Gbit/s line speeds.
This is the last Special Report that Ray Weiss, who passed away on New Year's Eve, prepared for us. We will miss his insight, his expertise, and his friendship. (See our tribute to him in our February 4, 2002 issue, p. 7.)—ED.
Silicon switch fabrics will form the core of next-generation mid- to high-end network switches and routers. Merchant switch-fabric chips are increasingly replacing proprietary ASICs and older switch fabrics. Next-generation switches and routers will deploy in one to two years and build on emerging, high-performance backplane switch-fabric chip sets with throughputs of 160 Gbits/s to Terabits/s. They will support 2.5-Gbit/s OC-48, 10-Gbit/s OC-192, and 10-Gbit/s Ethernet, with headroom for future line speeds.
Backplane switch fabrics provide the switching needed between arrays of line cards for network switches and routers. Generally deployed as chip sets, they deliver cost-effective performance for layers 2 and 3 switching and routing. They also provide an upward migration path from OC-12's 622-Mbit/s and OC-48's 2.5-Gbit/s line speeds, to higher-bandwidth lines such as OC-192's 10 Gbits/s and future 40-Gbit/s OC-768.
A migration path is needed. It takes one to two years to design, test, and initially deploy telecom switches and routers, which in turn have field lives of seven to 10 years. Thus, there's a dichotomy between the telecom switch and router life cycle and silicon ICs that, by Moore's law, double every 18 months or so in performance and functionality. Consequentially, silicon doesn't continually move into the telecom sector. Instead, silicon insertion moves in spurts and jumps where each insertion defines architectures that must serve multiple generations of line speeds.
A window is now open for current silicon insertion, providing the technology base for next-generation mid- to high-end switch and router architectures. To fill that window, new backplane switch-fabric chips, some on 0.13-µm CMOS, are coming online. Switch/router designers have a range of switch-fabric cores to choose from.
Backplane switch fabrics are a specialized form of switch fabric dedicated to a single task: connecting line cards via a switch across a virtual backplane. Traffic from one line card is moved through a switch and passed to the proper output line card—hence, the term "backplane switch fabric." But multiple backplanes, and even multiple boxes, can be in a chassis for a switch—thus the term "virtual backplane." These boxes can even be separated. For example, Mindspeed's Cx27300 chip set supports box interconnections of up to 30 m. Plus, PMC-Sierra's ETT1 chip set supports up to 70-m connections with its LCS protocol.
Switches and routers switch inputs to outputs. Switches work at a lower level, usually with common subunits as in a LAN. A router classically switches between different subunit classes, like LANs to MANs, the core to MANs, and so on. Also, both switches and routers have some form of quality-of-service (QoS) flow control. It may go beyond the classic OSI layer 2 or 3 processing definitions. Switches and routers are supported by backplane switch fabrics.
Conceptually, switching and routing are simple. Just take incoming traffic— time-division multiplexing (TDM), ATM, IP, Frame Relay, and Gigabit Ethernet—and encapsulate it into one or more packets or cells. Then, switch it to the addressed output line card, where it's reformatted and transmitted. A classic router architecture contains multiple line cards, within onboard queue managers (QMs), that connect to a central switching mechanism (Fig. 1).
Newer switch fabrics are protocol agnostic: they handle multiple protocols, first converting them into an internal cell or packet format for switching, then converting them to the output protocol. Switches and routers thus bridge traffic between different protocols.
Line cards and a central switch compose those switch/router systems. The line cards take in line-speed data, convert it (PHY MAC, or physical-layer MAC), and feed it to a processing block made up of a network processor (IC or ASIC) or a traffic manger. The block outputs the traffic as standardized cells in a format like CSIX or SPI-4, which are fed into the switching system.
Typically, the switching system consists of a front-end/back-end QM and a switching mechanism. Generally, the line card includes the QM, which links to one or more switching cards via the backplane. Some switch fabrics have the QM on the switch card. Others, like IBM's PowerPRS Q-64G switch chip and Internet Machines' CE200, integrate the QM into the switch chip itself.
A high-speed serial bus generally connects the QM and the central switch to minimize connection pin count—critical because most backplane switch fabrics are single-level switches comprising stacked switch chips. For a line card input to be switched to every possible output port, it must have a link to each switch chip in that switch stack.
Silicon has simplified switching implementations. Most newer backplane switch fabrics have integrated the serializer/deserializer (SERDES) into their QM(s) and the central switch chips. Also, higher silicon and packaging densities have led to wider output sets and larger crossbar switch arrays. QMs typically now field 32 or more serial outputs. Switches with 32-by-32 or 64-by-64 arrays are becoming the norm.
Not all fabrics break down into QMs and switch chips. Internet Machines' CE200 and others integrate everything onto a single stackable switch chip. Some, such as IBM's PowerPRS Q-64G, move the queues to the switch element. Others do a low-level switch implementation of their chip set. For instance, Agere's PI140xx switch fabric includes the PI140XS, a standalone switch that has queues with 32 ports supporting a 40-Gbit/s switch.
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