Until recently, statistical static timing analysis (SSTA) had been the darling of EDA-centric technical conferences and symposia for several years. At those conferences, SSTA was touted as "The Answer" to the most vexing problem facing the semiconductor industry: the inability of traditional corner-based signoff methodologies to keep up with the effects of process variability on yields and performance.
But, alas, the hype surrounding SSTA is beginning to die down. There's little room left for innovation in the fundamental algorithms for statistical analysis, so the technical conferences are moving on to other emerging technology topics. However, as 65-nm processes become the high-end mainstream and 45-nm lines are being shaken out, the questions surrounding process variation loom larger than ever.
Good old-fashioned static timing analysis (STA) based on process corners remains the bedrock methodology for design teams signing off on 65-nm projects. While no one is abandoning STA just yet, designers are starting to realize that SSTA can be a valuable addition to their signoff flow. And although the basic technology of SSTA is more or less stable, infrastructure support is shaping up.
So who's using SSTA, and how? What's going on with statistical models and cell characterization? Should design teams look at it for their next-generation designs? Consider this a followup to an earlier report on SSTA, in which readers can find more basic information (see "Timing Analysis Rounds The Corner To Statistics" at www.electronicdesign. com, ED Online 11664).
A use model emerges
SSTA's path from conference topic to practical technology has been slower than anticipated, perhaps painfully slow for the EDA vendors who have invested in it.
"SSTA has been typical of many emerging EDA technologies over the years," says Tom Ferry, vice president of business development for signoff products at Magma Design Automation. "At first, there's lots of hype. Then people look more closely and realize it's more difficult than they thought."
For Synopsys, which released its PrimeTime VX and Star- RCXT VX statistical signoff tools at DAC in 2006, adoption of statistical timing signoff has reflected this pattern.
"It's a matter of trust," says Robert Hoogenstryd, director of marketing in Synopsys' Implementation Group. "People aren't abandoning their traditional signoff flows. But people are beginning to invest in SSTA at 65 nm."
Further, says Hoogenstryd, many would-be adopters are still on the learning curve. "Some companies are using the 65-nm node as an experimental or test platform for SSTA and are really targeting deployment for production at 45 nm," he says.
The emerging model uses SSTA alongside corner-based STA. According to both Magma Design Automation and Synopsys, SSTA customers continue to sign off on their designs with traditional process corners and derating. They'll use SSTA in parallel with that flow to build confidence in it and get a feel for how statistical results correlate.
Incremental adoption
Given that few, if any, design teams will be dropping their existing signoff flows, SSTA adoption will incrementally creep into design methodologies.
"Instead of going from plain-vanilla STA plus signal integrity to full-blown SSTA, you can take some incremental steps to minimize the disruption in your flow and adopt some value," says Magma's Ferry.
An incremental and limited adoption of SSTA can enable designers to reduce the pessimism imposed by traditional static- timing flows. In such flows, variation is represented in terms of process, voltage, and temperature (PVT) and gets lumped into a global parameter known as on-chip variation (OCV).
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