[Design View / Design Solution]
Designing A Multi-Gbps Memory Interface Requires Scrutiny
DDR3 and XDR DRAMs offer solutions to multi-gigabit-per-second interface issues, but comparisons are necessary to select the right one for a given main memory or consumer application.
Popular consumer electronics products like gaming consoles, digital TVs (DTVs), and PCs offer more features and greater performance with each successive product generation. The data-intensive nature of these products tightly links the capability of their DRAM memory interfaces with the ability of the product to support larger feature sets and greater performance.
Multi-gigabit-per-second (multi-Gbps) memory-interface architectures enable these products to achieve the function and performance required. However, memory-interface designs must overcome significant challenges so that product performance and quality can be attained.
Newer-generation DDR3 DRAM and XDR DRAM physical-layer interfaces (PHYs) are tailored with special features to overcome the challenges and issues posed by multi-Gbps memory-interface architectures. But DDR3 and XDR DRAMs have attributes that suit them to certain application classes.
In digital TV applications, for example, XDR DRAMs hold cost and certain design advantages over DDR3. On the other hand, DDR3 is well-suited for designs needing high capacity at the lowest cost-per-bit of storage. Like its DDR2 predecessor, DDR3 is a high-volume commodity DRAM that provides as much capacity as the system designer requires at the lowest possible per-bit cost.
Yet if high capacity at a low cost-per-bit isn’t the principal design metric, XDR DRAM can be a better choice, especially for consumer electronics applications like DTV and HDTV. These particular designs require high bandwidth and small access granularity, but don’t need high capacity.
For example, a typical DTV application requires 6.4 Gbytes/s. This can be achieved with either two 512-Mbyte x8 XDR DRAM devices (providing 128 Mbytes of capacity, with a desirable 16-byte access granularity) or with four 1-Gbyte x8 DDR3-1600 devices (providing 512 Mbytes of capacity, with 32-byte granularity). In such systems, an XDR solution better matches the system’s bandwidth, capacity, and access-granularity needs in comparison to DDR3. As will be discussed later, it becomes clear that an XDR DRAM can actually be less expensive as well—not in terms of cost-per-bit, but in overall system terms, including component count, board complexity, and design time.
Demanding Physical Effects When engineering multi-Gbps interface architectures, the design must be able to overcome physical effects that degrade signal timing and voltage margins, and hence, constrain the system’s performance. Those physical effects are well-known to seasoned system designers—over generations of new designs, they’ve faced and ultimately resolved them to maintain signal integrity. But for multi-Gbps interface designs, those issues are exacerbated, becoming more challenging and demanding newer solutions.
For example, multi-Gbps signaling suffers substantial degradation due to transmission-line discontinuities. These discontinuities appear in several places in a typical memory channel, from the memory-controller silicon’s attachment to its package, to the package attachment to the board, and on to the board-level imperfections in the transmission line. Even more disruptive discontinuities appear in the DRAM side of the channel, especially if memory module sockets are employed.
These many sources of impedance discontinuity in a memory-channel transmission line create reflections, which high-speed IO designers will recognize as a form of signal interference known as “inter-symbol interference” (ISI). Here, the channel appears to have residual memory, such that information in a previously transmitted bit ends up adversely affecting information in a newly transmitted bit.
Treating a memory-channel as a transmission line faces other challenges, too. For instance, a 50-Ω terminator for a 50-Ω transmission-line receiver is meant to perfectly match transmission-line impedance, eliminating reflections and the resulting ISI. Even with modern on-die termination schemes, though, it’s impossible to achieve perfect impedance matching, because the transmission line has so many discontinuities.
Furthermore, perfect on-die impedance can’t be attained due to the parasitic input capacitance (or CI) of the on-die receiver. This causes a 50-Ω resistor to appear non-ideal at higher frequencies, again creating reflections and ISI.
Impedance discontinuities and ISI effects like these don’t present major issues at sub-gigabit-per-second transmission rates. However, it’s a different story at multi-Gbps rates, where 625-ps data eyes are common. If terminations aren’t matched, if too many discontinuities are in the channel, or if CI is too high, the ideal 625-ps data eye the designer hopes to transmit becomes a 300-ps eye opening by the time it reaches the receiver.
Additionally, electrical traces on the board involve other parasitic capacitances, hence a natural amount of signal attenuation. For instance, a signal may start out with 500 mV of signal amplitude, but the electrical system transporting that signal acts like a low-pass filter. As signals propagate increasingly faster, the total amount of energy arriving at the receiver is substantially less than that which was originally transmitted. The result is the original 500 mV may appear closer to 200 mV due to natural channel attenuation.
The channel-equalization techniques commonly used to address this high-frequency attenuation in high-performance SERDES applications may not be applicable to DRAM systems. That’s because the I/O circuits of such systems must be optimized for latency, power, and cost, ruling out the use of most well-known equalization techniques.
Crosstalk is another major cause of signal degradation, involving undesired capacitive, inductive, or conductive coupling from one signal pair to a neighboring one. Crosstalk is, in fact, the major reason for speed limitations in single-ended signaling systems such as DDR3 (or its higher-speed cousin, GDDR3). Because XDR DRAMs utilize differential signaling (similar to high-performance SERDES systems), they are orders of magnitude more resilient to crosstalk emissions than DDR3 DRAMs.
Consequently, single-ended signaling must address crosstalk with an assortment of design techniques that isolate signals at the board level. As data rates rise, designers must physically separate electrical channels increasingly further apart to avoid crosstalk effects. In other words, designers must engineer a more expensive transmission-line system between transmitter and receiver, and between controller and DRAM, to accommodate single-ended signaling at multi-gigabit data rates.
Differential signaling also offers a cost benefit in terms of memory-controller package cost. A memory-controller ASIC package with 200 memory I/O, for instance, is substantially cheaper using wirebond packaging versus flip-chip packaging. Such a cost benefit is highly appreciated in cost-critical consumer applications like DTVs.
I want faster and faster memory on my PC because I need it to run my real-time audio effect software, I'm sure everything will be better in the future. ---- http://www.softhardzone.com ----
Hamuro -December 18, 2007
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