[Engineering Feature]
High Efficiency Challenges Power-Management Design
Designers face the formidable task of providing high-efficiency power management for processors that operate at 1 V and below, at 100 A or more, and at gigahertz frequencies.
The semiconductor industry has always forced the power-supply industry to follow its trendsetting lead. For the last decade, that trend has been to cram more transistors into a single package, particularly microprocessors. This led to microprocessors with smaller feature sizes and tighter spacing between internal components. To be operational, smaller feature sizes forced the processors to operate at a lower voltage. This, in turn, required lowervoltage power supplies with greater design challenges than their predecessors of five to 10 years ago.
Designers can deliver low-voltage, high-current microprocessor supplies. But when you add the requirement for high efficiency (90% or better), the technology falls a bit short. It’s unlikely that the high-efficiency requirements can be met using present-day components and technologies, but it can reach about 70% to 80%.
To understand processor power-source requirements, check out the 2006 International Technology Roadmap for Semiconductors (ITRS). It projects operation at 1 V and currents in the 100-A region for processors in the year 2010. By 2020, the expected supply voltage will be 0.7 V at higher currents.
A voltage regulator-down (VRD) configuration with all of its components mounted directly on a computer’s motherboard now powers most processors. Most VRDs have an 8-bit voltage identification (VID) code whose eight input lines connect to the corresponding eight VID pins of the processor.
By sensing the microprocessor’s VID code, the voltage regulator sets the required operating voltage for the processor. The processor also can employ dynamic voltage identification that allows it to vary clock frequency and operating voltage “on the fly,” in response to the processor’s workload and the thermal environment.
Intel’s November 2006 Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines (www.intel.com/design/processor/applnots/313214.htm) is an example of present-day processor power management. These powersource design guidelines are for five different processors:
Maximum supply voltage: 1.4 V to 1.425 V
Maximum current: 75 A to 125 A
Tight output voltage regulation (±5%) under all line, load, and environmental conditions
Very low ripple, typically less than 10 mV rms p-p
Efficiency of 75% to 80%
Fast transient response, consistent with microprocessor clock frequency
Overvoltage protection
Overcurrent (short circuit) protection
Overtemperature protection
Thermal management of power-dissipating components
Relatively small package size so that the supply can be located close to its microprocessor load.
MULTIPHASE CONVERTER ICS The only topology that can meet today’s processor power needs is the multiphase switch-mode converter. It employs two or more identical, interleaved cells connected so that their output is a summation of the outputs of all cells (Fig. 1).
To understand the advantages of the multiphase converter, look first at the shortcomings of singlephase converters relative to supplying high current and low voltage. With a conventional single-phase converter, the output ripple and dynamic response improve with increased operating frequency.
In addition, the physical size and value of the output inductor and capacitor shrink at higher frequencies. Unfortunately, after the frequency reaches a certain limit, the converter’s switching losses increase and its efficiency declines. This forces a design tradeoff between operating frequency and efficiency.
To overcome these single-phase frequency limitations, the multiphase cells operate at a common frequency, but are phase-shifted so that conversion switching occurs at regular intervals controlled by a common control chip. The control chip staggers the switching time of each converter; therefore, the phase angle between each converter switching is 360°/n, where n is the number of converter cells. Because cell outputs are in parallel, the effective output ripple frequency is n × f, where f is the operating frequency of each cell. This provides better dynamic performance and significantly less decoupling capacitance than a single-phase system.
Current sharing among the cells is necessary so that one cell does not “hog” too much current. Ideally, each multiphase cell should consume the same amount of current. To achieve equal current sharing, the output current for each cell must be monitored and controlled.
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