In its CoreCreator II, which comprises verification IP and command-line based tools for validating Open Core Protocol (OCP) implementations, the Open Core Protocol International Partnership (OCP-IP) hopes to reduce system-on-a-chip (SoC) design time and risk while improving time to market.
CoreCreator II allows users to verify, debug, and analyze OCP Cores and OCP-based systems. It is comprised of two fundamental component parts: Synopsys’ DesignWare verification IP which generates and responds to all types of OCP 2.2 transactions. The monitor provides coverage reports of the functional coverage groups defined in section 4 of the OCP-IP compliance check document. Second, the Sonics’ performance analyzer (ocpperf2) and disassembler (ocpdis2) measure system performance and help view the behavior of the OCP traffic.
The new version is compatible with traditional Verilog and VHDL testbench environments to create directed tests for OCP-based designs. Synopsys DesignWare verification IP within CoreCreator II adds support for advanced verification methodologies as described in the Verification Methodology Manual for SystemVerilog to enable its use in constrained-random verification environments.
CoreCreator II includes support for the existing CoreCreator BFM Verilog task interface allowing members to transition testbenches to the new verification IP with minimal changes to their testbench code.
OCP-IP members receive free training and support, as well as software tools including CoreCreator—enabling them to focus on the challenges of SoC design. Leveraging OCP-IP’s infrastructure eliminates the need to internally design, document, train and evolve a proprietary standard and accompanying support tools, freeing up critical resources for the real design work, while providing enormous cost savings.
Members can now request copies of CoreCreator 5.0 as part of the benefits of their membership agreement by visiting the OCP-IP Web site.
Open Core Protocol International Partnership
www.ocpip.org
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