Reprints     Printer-Friendly    Email this Article    RSS        Font Size     What's This?

[Web Exclusive]

Router Boosts Analog Routing Productivity For Matched Devices



Staff  |   ED Online ID #18485  |   March 17, 2008

Article Rating: Not Rated

Laying out matching devices in custom analog circuits is an error-prone, time-consuming job that can kill analog design yield. Such devices can comprise up to 40% of the devices in a circuit. Silicon Canvas’ matching device router, Laker-MDR, facilitates the special routing requirements of analog-matching devices and automatically generates electrically equivalent routes free of design-rule errors. Customer benchmarks using Laker-MDR demonstrate productivity increases of eight-to 10-times when compared to traditional methods, it’s claimed.

In order for devices to match electrically, the physical layout requires close proximity and interconnect (routing) that is electrically identical while still meeting a myriad of constraints and advanced design rules. Laker-MDR honors a broad range of constraints while automatically generating routing for matched devices free of design-rule errors.

By using special layout techniques analog designers can minimize the effects of process variability on matched devices. Common methods include the use of folded or multi-fingered transistors; splitting transistors into multiple gates with symmetrical; offset segments and identical layout; adding dummy gates; and sometimes all of the above. The Laker-L3 (layout) tool has specialized software for generating these kinds of layouts. Then Laker-MDR is used to provide the matched device routing.

Laker-MDR is an option to the Laker design-driven layout (DDL) suite of automated custom layout software that includes the Laker Constraint Editor/Extractor; a constraint-driven Custom Placer; and custom router software for analog layout designs.

Laker- MDR is available now and starts at $37,500 for a one year TBL.

Silicon Canvas Inc.
www.sicanvas.com




Reprints     Printer-Friendly    Email this Article    RSS        Font Size     What's This?


  • Network-On-Chip Tools Arrive for The Masses
  • Tackling System Design Challenges Through Early Verification
  • ESL Tools Take Center Stage As Designers Move Up
  • Parasitic Extraction Tool Targets Next-Generation Custom ICs
  • Synopsys Jumps Into ESL-Synthesis Pool
  • Verify Control Systems Before Committing To Hardware
  • You're Using How Many FPGAs?
  • Tool Up For The FPGA Blitz
    1) Build A Smart Battery Charger Using A Single-Transistor Circuit
    (187 views today)
    2) Hot Hands For Some Cool Rock: Motion Sensing Meets Audio Engineering
    (170 views today)
    3) What's All This Transimpedance Amplifier Stuff, Anyhow? (Part 1)
    (91 views today)
    4) GPS-Derived Grandmaster Clock Delivers Ultra-Precise Time And Frequency Sync
    (90 views today)
    5) Downconverting Mixers Lower Power Consumption While Improving Performance
    (71 views today)
    ALL TOP 20







    POST YOUR COMMENTS HERE

    Name:

    Email:
    Rate this article:

     less useful more useful 
    1
    2
    3
    4
    5
    Your Comments:

    Enter the text from the image below




    Please refresh the page if you have trouble reading this text.
    (Acceptable Use Policy)
     
     

    PartFinder

    Find real-time pricing, stock status, same-day/next-day shipping options and more. Brought to you by Digi-Key. Go to PartFinder.    
    GlobalSpec

    PART SEARCH :
    Powered by: GlobalSpec - The Engineering Search Engine
    Sponsored Links

    Electronic Design Europe Electronic Design China EEPN Power Electronics Auto Electronics Microwaves & RF
    Mobile Dev & Design Schematics Find Power Products Military Electronics EE Events Related Resources