At the inaugural Design Automation Conference in 1964, then known as the SHARE Design Automation Workshop, the fledgling design-automation industry batted around some of the fundamentals of its mission to engineers. Papers carried titles such as “A method for best geometric placement of units on a plane,” and “New horizons in graphic output on the IBM 1403 printer.” Some of that year’s program hinted at yet unformed methodologies.
Now, as the EDA industry heads for the 45th Design Automation Conference (DAC, Anaheim, Calif., June 8-12), the focus is squarely on methodology. “In putting together this year’s program, we relied on two years’ worth of attendee surveys and feedback,” says Limor Fix, 45th DAC General Chair (see “Anatomy Of A Conference Program” at www.electronicdesign. com, Drill Deeper 18940). “People want more methodology- oriented content and more ‘how-to’ with today’s tools. The feedback was that there was too much future-oriented content and not enough hands-on tutorial information.”
So in accepting some 20% of the 639 paper submissions, DAC’s program committee forged a technical conference heavy on the methodological aspects of areas that should interest power users of EDA tools. Domains with the greatest number of paper submissions include system-level design and hardware/software co-design, physical design and manufacturing, low-power design and power analysis, timing analysis and design for manufacturing (DFM), and verification. All are well represented in the program.
“These five broad areas provide a good indication of what the industry is looking for and what academia is doing. It shows where the focus and money is going,” says Fix.
SYSTEM LEVEL HEATS UP
The electronic system level (ESL) features a number of growing areas for designers. One is the design of systems-on-a-chip (SoCs) with multiple processors and the creation of parallelized software to run on them (see “Software Rules The Day In Multicore SoC Design,” Electronic Design, April 24, 2008, p. 38, ED Online 18640).
Tutorials, panels, paper sessions, and invited papers at DAC will present new ideas, state-of-the-art design tools, and novel methodologies to reduce development time, reduce energy consumption, and enhance system performance of these complex designs and embedded parallel software.
Tools for power optimization at ESL have been emerging for a few years now. At DAC, ChipVision Design Systems will unveil two new ones for helping designers meet their power budgets early in the design cycle.
One, dubbed PowerOpt, lets RTL and system designers work interactively with system-level descriptions written in ANSI-C, SystemC, and C++, exploring and visualizing critical tradeoffs in timing, area, and power. It then implements their choices to generate power-optimized, register-transfer-level (RTL) code with up to three times lower power consumption than RTL flows.
ChipVision’s second new technology to appear at DAC is the P-SAM (Power Simulation, Analysis and Modeling) framework. It offers system-level designers and software developers a standards-based application programming interface (API)
for source-code instrumentation, as well as comprehensive analysis tools for design descriptions in SystemC or pure C/C++. It also enables early system-level power analysis based on system-level simulation.
Working interactively, PowerOpt and the P-SAM framework perform architectural, software, and power tradeoff analysis at a level not typically possible with other approaches (Fig. 1). Users can investigate various bus topologies, compare power consumption of intellectual-property (IP) blocks, identify hotspots, and explore other system areas to hone their power-management strategies and verify these are met.
Both PowerOpt and P-SAM are available now. PowerOpt costs $450,000 for a three-year, time-based license. P-SAM pricing varies depending on the SoC’s structure.
HIGH-LEVEL SYNTHESIS GROWS
Another product that can provide gains in power management at ESL is version 3.4 of Forte Design Systems’ Cynthesizer SystemC synthesis tool. Cynthesizer 3.4 adds integration with a poweroptimization tool.
Power-estimation reports generated by the power-optimization tool are included in the results available with the Cynthesizer Workbench, Cynthesizer’s graphical interactive analysis environment. These reports, cross-linked to annotated source-code views, make it easy to understand implementation tradeoffs and make changes for improved quality of results (QoR).
Given the increased interest among designers in FPGAs, it’s only logical that high-level synthesis should make its way to FPGA flows. At DAC, Synfora will show its PICO Extreme FPGA and PICO Express FPGA algorithmic synthesis tools. The PICO Extreme FPGA makes it possible to implement dramatically larger and more complex subsystems using a recursive system-composition methodology. It allows for familiar design styles, reduces runtime, and achieves high QoR in implementing video codecs, wireless modems, or imaging pipelines. PICO Extreme’s recursive system-composition methodology is enabled by tightly coupled accelerator blocks (TCABs) that allow users to designate parts of their algorithm as custom building blocks.
PICO Express FPGA is a flavor of the tool optimized specifically for Xilinx’s 65-nm Virtex-5 and Spartan-3A DSP FPGAs. All products are currently available. PICO Extreme starts at $350,000, while PICO Express FPGA starts at $150,000. Standards in the ESL realm continue to evolve, and DAC will be the venue for the Open SystemC Initiative’s (OSCI’s) rollout of the final version of TLM 2.0. This standard enables SystemC model interoperability and reuse at the transaction level, providing an essential ESL design framework for architecture analysis, software development, software performance analysis, and hardware verification.
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