Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to guarantee interoperability when different memory devices are used together and that they work when powered up. Fundamentally, interoperability begins at the physical layer.
For a DDR memory interface, the responsibility of good physical-layer performance falls at the hands of the design engineers and implementers, whether they’re developing a DDR memory controller, chip, or system. Other standards such as USB, PCI Express, SATA, or fully buffered DIMM (FBD) have dedicated standard bodies that govern how to carry out compliance testing. DDR memory testing, on the other hand, is unique because JEDEC doesn’t enforce a compliance program—it expects adopters to perform the compliance measurements themselves.
One common measurement method for compliance testing is eye-diagram analysis. This method provides a comprehensive analysis of a DDR memory’s waveform signal integrity by looking at the eye characteristics. Through the eye diagram, you can quickly gauge the amount of jitter on the device, if there’s any glitch or non-monotonic edge, and other problems on the device.
This article will highlight some of the eye analysis methods you can find with the oscilloscope as well as the logic analyzer. It also discusses some of the debugging capabilities of the instruments when problems are found while performing eye-diagram analysis.
QUICK EYE-DIAGRAM SCAN
A DDR memory interface can be made up of many DQ (data) channels. For instance, a DDR DIMM (dual-inline memory module) consists of 64 DQ channels that equal 64 bits or 8 bytes. The logic analyzer is the best tool to take a first glance at the signal-integrity performance due to its high input channel count. Comparatively, an oscilloscope has only four channels. Logic analyzers don’t feature the oscilloscope’s sampling or vertical resolution, but some can build rough eye diagrams instantaneously across all input channels (Fig. 1).
An interposer probe is inserted between the DIMM and connector. Signals are routed through the probe to the logic analyzer. With an oscilloscope, the scope probe will likely need to be switched from signal to signal, which can be cumbersome and time-consuming if you want to look at the overall approximate signal-integrity performance. Once the eye diagrams are constructed, you can analyze each data line to look for any problems and use an oscilloscope to help you further debug the issue.
Besides that, the eye diagram is also helpful for adjusting the logic-analyzer sample position to the center of the eye opening for functional analysis. This helps avoid sampling waveforms during the transition state or outside the data valid window where wrong data could be captured.
OVERLAY BIT EYE-DIAGRAM ANALYSIS
The overlay bit eye diagram analyzes each individual bit of a read or write burst. Since the DDR memory controller and chip use the same DQS (strobe) and DQ (data) bus for communication, the oscilloscope has to trigger at the beginning of the read-only or write-only waveforms. This can be easily performed using the zone-trigger capability available on some oscilloscopes.
With the zone trigger, you can determine and draw zones on the oscilloscope screen to visually determine the event identification condition. Such capability makes it possible to track the signal of interest, depending on whether or not the waveform intersects the zones.
On a memory interface, the read and write signals exhibit different signal characteristics on both the DQS and DQ. Therefore, in this case, the zone trigger can be used effectively to separate and trigger the signals at the beginning of the read or write burst (Fig. 2).
After successful setup of the zone trigger, the oscilloscope display can be set into infinite persistence and color-graded mode so that the waveforms will overlay and build up on the screen, creating a stream of eye patterns along with waveform intensity information. Then the eye diagram gets scanned for each individual bit and for any problems such as glitch, overshoot, or signal anomalies.
To get a quantitative view of signalintegrity performance, other measurements can be applied to the eye-diagram pattern, including eye height, eye width, signal amplitude, and slew rate. The measured values can then be compared with the JEDEC specification.
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