[Technology Report]
The Embedded Plan For JTAG Boundary Scan
The decades-old standard spawns new design-for-test applications and opens the door to embedded instrumentation.
In 1990, the IEEE ratified the 1149.1 standard known as boundary scan. Developed by the Joint Task Action Group (JTAG), it was created to help solve the overwhelming testing problems caused by ever-increasing larger-scale ICs and densely packed multilayer printed-circuit boards (PCBs).
The old “bed of nails” method of testing PCBs no longer worked as well, and the inaccessible circuits and even pins on ICs made testing difficult if not impossible. With boundary scan, IC and board manufacturers could provide fully automated testing.
The standard has been regularly updated over the years, and a whole infrastructure of hardware and software manufacturers has emerged to support testing efforts. Thanks to recent changes, the standard is part of embedded design platforms. Boundary scan now lies at the heart of a new test and measurement approach called embedded instrumentation.
WHERE JTAG FITSITS IN In the past, the board would have gone directly to a functional test, where it would be hooked up to power and stimulation signals to see if it worked as designed (Fig. 1). The test would be run at normal design frequencies and speeds. Such a test was performed on a bed-of-nails type of in-circuit tester (ICT). Defects were discovered and repaired.
However, years of test experience have shown that most failures are structural. Some statistics say that more than 99% of all faults lie not with bad ICs or design errors, but with PCB and solder defects such as unsoldered joints, cold solder joints, lifted pads, bridged solder connections, reversed parts, and other physical problems. That’s why most complex boards go through testing that detects such structural problems before the functional ICT.
For example, after the assembly of the complex PCB, a first step is visual inspection. An engineer may manually and visually look at the board to see if all of the parts are there and that they’re oriented properly and soldered correctly. This step may also include optical machine-vision inspection and/or X-ray inspection. Both are useful in detecting initial faults, including poor or missing solder connections.
A structural test is next. This is where boundary scan comes in. It provides a way to do a thorough test for opens, shorts, and missing connections, as well as bad solder connections not identified by other means. With boundary scan, this testing is automated with problem areas identified to make quick repairs and corrections.
After that, the usual functional testing occurs. This continues with ICTs or the bed-of-nails test heads that make contact with the board’s copper and solder connections to provide the test signals and measurements. After functional testing and repair, overall system testing is performed to conclude the process. Such system tests involve environmental evaluation as well as software and configuration processes.
JTAG STANDARD OVERVIEW The basic idea behind boundary scan is that because most points in an IC or on some PCBs are inaccessible, designers can build in test/access circuitry that will allow an engineer to read the status of a specific node or stimulate a node with an external signal.
Today, many (if not most) large-scale ICs, ball-grid arrays (BGAs), systems-on-a-chip (SoCs), ASICs, FPGAs, and multichip modules have boundary-scan circuits built in. High-density PCBs with multiple layers also represent a test problem. The concept is to build in a large number of these test access points so a complete circuit or part thereof can be tested externally.
Figure 2 shows the essential boundary-scan architecture. The block of logic in the IC to be tested is connected to multiple boundary-scan cells. The cells are created along with the IC circuitry when the chip is fabricated. Each cell can monitor or stimulate one point in the circuitry. With its flip-flops and multiplexers, the cell can be used for either parallel-in/parallel-out or serial-in/serial-out operations (Fig. 3).
The cells are then linked serially to form a long shift register whose serial input, designated Test Data Input (TDI), and Test Data Output (TDO) serial-output ports become the basic I/O of a JTAG interface. The shift register is stepped by an external Test Clock (TCK). To stimulate the circuit, test bits are shifted in. This is called a test vector.
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