[Design View / Design Solution]
Bulletproof Your System Timing With Programmable Clocks
By validating and then ensuring timing margin during development and production, programmable clocks help reduce system cost and optimize performance.
Ever wondered how much timing margin your system really has? You’ve probably asked some questions along these lines, such as: Does my crystal really need 20 parts-per-million (ppm) accuracy? What if noise couples to my timing clock edge? Will my display always look this good across manufacturing process corners? Is there enough timing margin to add spread spectrum (SS) for reduced electromagnetic interference (EMI)?
This article helps answer these questions by exploring the theoretical means for budgeting system timing. It also outlines empirical methods for creating and verifying timing margin using features of advanced programmable clocks.
Every digital electronic system requires a periodic signal or clock to initiate input data acquisition, data processing steps, and output data transmission. The input and output data can be represented by analog or digital signals, depending on which portions of the system are interfacing to the analog world or to another digital system.
When interfacing to the analog world, the system must have clock signals for the analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) used at the inputs and outputs. Timing error of the sampling clocks used in ADCs and DACs results in data distortion. The analysis of analog data distortion is also critical to proper system operation, but here we’ll focus on the system timing associated with the transmission and processing of digital data.
TIMING ANALYSIS The interfaces to digital systems require clocks to synchronize the transmission and receipt of data. When processing digital data, a clock is required to change the address pointers of the execution code and sequence data flow through the processing logic. A poor clock signal will create data-processing and/or datatransmission errors. Therefore, it’s necessary to carefully analyze the system timing requirements and select the proper timing components.
The traditional analysis method includes digital simulation of the toplevel system schematic using digital models of the subcomponents. However, this methodology doesn’t accurately model the effects of supply noise, coupled noise, actual timing generator characteristics, or advanced timing features like spread spectrum, which is used for EMI reduction.
To account for these effects, the system can be simulated at a frequency higher than the normal operating frequency to try and build in timing margin. However, the frequency delta is usually empirically determined from previous designs that worked with unknown margin plus some safety factor thrown in. Therefore, the resulting system is subject to timing failure within normal process distributions, in addition to unneeded cost increases for higher performance components than may actually be required.
A properly designed system uses timing references and distribution techniques that are accurate enough to ensure robust operation at all manufacturing corners without adding excessive cost. The cost analysis includes both the monetary cost of more accurate components and the expense of burning more power. Burning more power is an obvious issue for battery-powered systems, but it is also important for plug-in systems due to the incremental cost for increased capacity of the power supply and cooling components.
An extreme, brute-force example of maximizing timing margin in a system would be to use expensive third overtone crystal oscillators with differential 50-O outputs for each frequency on a board having six or more layers. This will shield the clock traces from noise and reduce EMI. Fortunately, the requirement for this level of timing accuracy and expense is extremely rare.
Making the accuracy versus cost tradeoff requires precise budgeting of the timing error from various sources. However, all too often, the inaccuracy of the timing models that are used in budgeting is only discovered during production. This subjects the program to a potential “lines down” situation when yields drop to unacceptable levels as a result of normal variations in components and process. If the timing margin could be verified during system development, the cost and performance can be optimized without compromising manufacturing yield.
A TYPICAL CASE The typical elements of a timing budget as well as sources of timing error for a system that’s transmitting data between two components clocked by two copies of the same reference clock are listed in Table 1. These represent the items that must be considered in a system transferring data from a transmitter (XMTR) to a receiver (RCVR). Because most of the noise is correlated, each error item in the table must be added directly rather than using an rms value to arrive at the minimum period for the system clock.
The table assumes that one or both of the components use an internal clock multiplying phase-locked loop (PLL) to operate at higher internal rates than the externally applied reference clock. Systems with these types of components require special attention, since this can result in additional timing error.
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