What’s a multiservice router/ switch? Multiservice routers and switches are network devices that support multiple switching and routing protocols, typically adding Multiprotocol Label Switching (MPLS) and Asynchronous Transfer Mode (ATM) switching to basic Internet protocol (IP) routing services (see the figure).
From an IT-services (information technology) standpoint, that means transparently supplying analog voice, fax, and Voice-over-IP (VoIP) capabilities simultaneously with basic data services. From a hardware standpoint, it implies autosensing services such as various high-speed versions of Ethernet SONET, Fibre Channel, T1/E1, and older modes. It also suggests a considerable challenge extracting clock and data signals from all those inputs.
Indeed, it is a challenge. Yet none of the base frequencies for the various standards are harmonically related. For Gigabit Ethernet and 10-Gigabit Ethernet (10GE), they are 625.000 and 644.53125 MHz, respectively. For SONET/SDH, the base frequency is 622.08 MHz. For Fibre Channel, it is 657.421875 MHz. Each of these frequencies is further complicated by adding a forward error correction (FEC) factor. While FEC ratios are established as standards, there are several possibilities, such as 255/238, 255/237, 15/14, and 239/237.
How have clocks in multiservice routers been implemented? Because of the different standards, OEMs initially found it necessary to build families based on separate models with different input configurations. More recently, market pressures have led to a common platform approach.
Historically, the clocking approach provides a separate voltage-controlled crystal oscillator (VCXO) for each clock. The required VCXOs are fairly expensive and tend to be among the least reliable parts in the system. Since all but one of these devices sit idle at any one time, it is a natural place to look when trying to optimize the system design.
This definitely presents a challenge to bringing data in from multiple standards and translating that data to a single format at some point. Consider Fibre Channel, where the lowest common sub-multiple of any of the other frequency options is a very small number. So, existing Integer-N phaselocked loop (PLL) approaches that are readily available cannot translate with precise accuracy.
It recently has become possible to simplify clocking design with chips that accept two reference input signals and generate output signals that aren’t harmonically related to those inputs. This facilitates translation between any two standard network rates.
What does that mean in practical terms? It makes it reasonably straightforward to achieve the basic functions of switchover when a reference signal changes and of holdover when a reference signal drops.
Switchover is the key to handling multiple services. As the references change, the clock device must switch over seamlessly. It is essential to design the switchover function so no runt pulses or extra-long pulses result from this change and no downstream PLLs will lose lock, even when no predefined relationship exists between the phases of the various reference input signals. It is additionally desirable to have a smooth phase transition during switchover. When a clocking system supports “smooth phase transition,” there is a gradual transitioning of the phase of the output signal as the device adjusts to the phase of the newly active reference. The system designer should be able to choose how fast this transition occurs to prevent a phase change greater than the system can handle while allowing for sufficiently fast settling to the new phase.
Not every system designer subscribes to that philosophy, of course. Some prefer a “no phase transition” policy, where the output phase won’t change even when switching between two references that aren’t phase-aligned. In that case, the output signal should show no sign that anything unusual has occurred to the reference input. The clock device should provide an alarm (sometimes a pin, sometimes a bit in a register map) to indicate to the system that a switchover has occurred if such information is important.
Holdover enables designers to build systems with greater uptime. Furthermore, it lets systems use reference signals that are intermittent or unreliable without fear of that unreliability crashing the system.
These new chips implement holdover by having the input PLL in the digitally controlled crystal oscillator (DCXO) employ an external crystal as its frequency source. That way, it continues to operate in the absence of the input reference signal. Absent that signal, the DCXO holds at the frequency it was operating at just prior to switchover until a reference signal again becomes available.
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