With no end in sight to the spiraling transistor counts in today’s bleeding-edge systems-on-a-chip (SoCs), the runtimes for EDA tools are rising in corresponding fashion.
If filling all of those gates isn’t enough to worry about, now designers have the additional drag on their productivity of waiting… and waiting… for place-and-route or physical verification runs to end. In the meantime, they hope and pray that after days, or even weeks, a given run won’t end up crashing or otherwise be unable to complete because of the tool’s inability to handle the capacity that’s been thrown at it.
EDA vendors’ days of leaning on systems houses to fix this problem through increases in system clock speeds have largely ground to a halt. But the systems houses have long since gone in another direction to overcome the clockspeed inertia, and that is to adopt multicore architectures. EDA vendors are responding with multithreaded applications meant to exploit the parallelism afforded by multiple processors, a trend that’s sure to accelerate in 2009.
SOME TRENDING TOOLS • One tool released late in 2008 that exemplifies this trend is Cadence’s Encounter digital implementation system, which promises users an overall productivity gain of about three times when multithreaded across four CPU cores (Fig. 1). A revamped memory architecture boosts performance capacity by about 40% on a single CPU. But the suite’s multicore backplane is what really delivers the scalability goods.
Floorplans for complex chip designs can take many months to create. Thanks to its multithreaded architecture, though, the Encounter system lets designers create multiple floorplans in parallel. This process can be driven by a given criteria, such as timing.
With total negative slack as a driving criterion, the system can generate up to 30 different floorplans and then rank them in terms of negative slack. This is the kind of power that multithreaded architectures can provide, and it’s likely to be the direction for EDA vendors across the board going forward.
As much as multithreading and multicore hardware architectures can aid in digital implementation, the benefits can be even greater in analog simulation applications. One promising startup, Gemini Design Technology, has brought multithreading to Spice simulation, touting a speed improvement of two to 10 times compared to single-threaded, Spice-accurate simulators (Fig. 2). The company says its tool has been benchmarked with circuits from 300 transistors to as many as 10 million elements on machines with up to 16 cores.
Gemini’s forthcoming simulator, which was expected to see initial production availability during the fourth quarter of 2008, approaches matrix solving by breaking up the overall circuit, sending it piecemeal to different processors, and then recombining the solved matrices into a seamless whole. Gemini claims it recombined the matrices with no introduction of error, a trick that has eluded those who have gone down this road in the past. Thanks to its adroit exploitation of multicore hardware, Gemini’s simulator will deliver broad performance scaling. Gemini believes that most applications can be handled by its simulator running on machines that have from four to 16 cores. Meanwhile, the simulator, as presently constituted, can output 64 threads, which prepares it for significant extensibility. With analog and mixed-signal content dramatically rising in SoCs, Gemini looks like a trendsetter among vendors of tools for analog simulation.
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