Depending on the type of product you're involved with, pc boards represent a range of design challenges. Generally speaking, you'd like to produce your board for as little money as possible, making sure that it's testable and manufacturable without hitches. It would also serve you well to look beyond the board itself at how it meshes mechanically with the rest of the system it's destined to be part of.
Yet in addition to those general engineering concerns, if you're looking at a board carrying extremely high-speed signals, board design presents some signal-integrity issues that could keep you awake at night.
One thing is certain: Boards are now more densely packed than ever. What constitutes the upper echelons of today's pc-board design work? The inner layers are being designed with trace widths of 4 mils and edge-to-edge spacing of 4 mils. On the outer layers, spacings are 5 mils (trace widths) and 5 mils (edge-to-edge spacing). These closely spaced traces open designers up to serious signal-integrity problems, with great potential for capacitive coupling and crosstalk between signals.
Not only are traces close together in the X axis, they're tight in the Z axis, too. The number of layers on boards varies with industry and application, but it's safe to put it in the range of 12 to 24 layers. You'll see as many as 50 in extreme cases, but that's the "lunatic fringe."
Then there are the devices with which boards are populated. Currently, ball-grid array packages sport 0.8-mm lead pitches with 1500 to 2000 I/Os. Pitches are getting tighter, though, with 0.5 mm on the way. That will translate into I/O counts of around 3000, leading board designers to perform even more fancy footwork to accommodate them while preserving signal integrity.
Along with spiraling density come increasing signal speeds and clock rates. On-board memory buses are running in the 500-MHz range with 1 GHz not too far off. In communications, the OC-48 communication protocol calls for data rates of 2.5 Gbits/s. That rate is heading toward 10 to 40 Gbits/s.
The result is digital signals that don't look like digital signals anymore. Multi-gigabit signals bring rise times of less than 100 ps. For a 10-Gbit/s signal, you could be looking at 25 ps. "A square wave is never perfectly square in practice," says Bill Wignall, president of Electronics Workbench. "There's overshoot, undershoot, ramp time, and ringing. Those effects are much more problematic if the speed at which the circuit needs to settle, or the time after which it's supposed to have reached its steady state, is shorter and shorter."
Thus, signal-integrity analysis be-comes a critical element in high-end pc-board design work. But it's not the only critical aspect. The tools must address other elements of the process well, even for boards that don't necessarily represent the cutting edge of design in 2002.
At the very outset of a board design, be mindful of partitioning. "Board design is not just a matter of buying components and sticking them onto the pc board and routing it," says Phil Loughhead, Protel product manager at Altium Ltd. "It's about designing a system or product, and there are a variety of ways you might choose to implement that product."
A particularly important element of the flexibility that designers must have in terms of partitioning and its impact on board design is the growing use of FPGAs. "The team doing the huge FPGA design is probably a completely different team than the one doing the high-density pc board," says Andy Watts, product marketing manager for solutions marketing at Mentor Graphics. "Traditionally, they have had different tool sets. All the timing constraints that affect the data, on and off that chip, have to be passed into the other flow."
Changes made in the FPGA's pinouts must be reflected in the board layout. Mentor's tools, for example, can take the pinout change data from the FPGA onto the board in a one-step process as opposed to doing it manually.
Altium's Protel DXP full-board-level design environment also supports FPGAs. The tool features macro libraries for Altera and Xilinx devices, which let designers work in the schematic paradigm inside the FPGA, and takes them straight to a place-and-route tool. Like the Mentor tools, it facilitates early partitioning of designs between programmable logic and other functionality on-board (Fig. 1).
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