A linear-recursive-sequence (LRS) generator produces binary sequences using a shift register and feedback through an exclusive-OR gate. The sequence length equals 2N1, where N represents the number of registers. The generator cycles through all 2N states, except one: the all-zero state.
If the LRS generator ever reaches the all-zero state, zero would be fed back to the input. Thus, the generator would be stuck here forever. Because the all-zero state could potentially occur after power is applied (when the contents of the registers aren't determined), it's necessary to detect the all-zero case and inject a logic "1" to produce the LRS.
Generally, a large OR gate (with N inputs), or a tree of two-input OR gates, detects the all-zero case. When N is large, however, this implementation proves slow and cumbersome. The circuit shown in the figure demonstrates an alternative method for detecting the all-zero case via a modulo-M counter, where M is greater than or equal to N. Here, U2 and U3 form a 15-bit shift register. The 14th and 15th bits of the shift register are fed back to its input through U4A, an exclusive-OR gate. This configuration forms the basic LRS generator.
When the generator is constructing an LRS, a logic "1" will always be produced before N clock cycles have passed. U4C acts as an inverter, connecting the bit sequence to the counter's (U5) reset pin. If the shift register contains a logic "1," the counter will be reset before the terminal count is reached. Because the terminal count output is always logic zero in this case, the feedback path through U4B isn't altered, and the LRS generation continues unaffected by the reset circuit.
But if the shift register contains all zeros, the U5 counter will reach its terminal count. This causes a logic "1" to be input to U4B, which further results in a logic "1" input to the shift register. Then the LRS is generated as usual.
Note that the 74LS163 counter powers up in an unpredictable state. Also, the terminal count may be reached even if the LRS isn't in the all-zero state immediately after power is applied. These factors could cause the LRS generator to be reset needlessly. Yet, that happens (at most) only once within M clock cycles after power goes on. Whether the LRS generator is reset due to the all-zero condition, or because of the unpredictable state of the counter after power-up, the LRS generator produces the correct sequence within M clock cycles.
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