Four to five years ago, the hype surrounding design-for-manufacturing (DFM) technology for advanced system-on-a-chip (SoC) design was near insufferable. At that time, 90 nm was the state-ofthe- art process node and most fabless houses were preparing for a shrink down from the 130-nm node. And without some way of feeding process parameters back into the design side, the likelihood of any chip yielding at 90 nm was slim to none.
This set off a bit of panic among the design community on the one hand and a feeding frenzy among venture capitalists and would-be DFM startups on the other. Indeed, a rather large number of startups emerged in the DFM space. Almost any tool that touched the back end was being called a “DFM” tool for one reason or another, speciously or not. Just as quickly, a backlash from the DFM-have-nots arose, with accusations of “design for marketing” hurled at those who didn’t fit into the more rigorous definitions of what DFM was supposed to be about. Today, with the 65-nm node firmly entrenched and foundries ramping up their 40-nm processes, the DFM picture has changed quite a bit.
The hype isn’t as strident these days, but that doesn’t mean it isn’t an essential element of SoC/ASIC implementation flows. In fact, it’s more vital than ever and will become more so with the coming process shrinks to 40 nm and below. DFM is even becoming a factor in analog/mixed-signal flows for RFICs (see “The Mixed-Signal Angle On DFM,”).
WHY DFM STALLED
The marketplace saw a surge of interest and activity in the DFM arena in 2004-05 (see “The Truth About Design For Manufacturing”). A number of startups appeared, such as Aprio, Blaze DFM, Clear Shape Technologies, Ponte Solutions, and Praesagus, all of which purported to hold the key to achieving acceptable yields at 90 nm and below. But some significant issues still had to be overcome.
For one, there was accounting for process data. “When people went to fabless or so-called ‘fab-lite’ models, they couldn’t do classic DFM,” says Michael Buehler-Garcia, director of DFM products at Mentor Graphics. “At IBM, process engineers could tune the process to handle the on-the-edge parameters of IBM’s own designs as opposed to changing the design to suit the process. But if you’re a small fabless house, it’s not going to be practical for a merchant foundry to adjust their process for your design.”
As a result, the fabless community often tended to grossly over-margin its designs to ensure printability. Designers would be forced to sacrifice area in the process, to say nothing of power and speed. But the inability to obtain foundry process data made efforts at yield optimization a shot in the dark at best.
Another significant roadblock to widespread DFM adoption was the fact that the raft of standalone DFM tools from the startups of 2004-05 were limited in terms of optimizing for yield. “The DFM startups saw the future but they lacked the back-end implementation piece,” says Dave Desharnais, group director of IC digital products at Cadence Design Systems. “The tools could tell you where things were going to be a problem but couldn’t tell the implementation flow how to fix it. So these guys were relegated to abstractly proving their technology to the physicists at these fabless companies.”
MAKING DFM VIABLE
Two things have happened since then to make DFM a viable technology. For one, the foundries, notably Taiwan Semiconductor Manufacturing Corp. (TSMC), have figured out a way to disseminate process data so EDA tools can use them without compromising their trade secrets. Second, those 2004-05 DFM startups with useful analysis capabilities were subsumed by the EDA industry’s RTL-to-GDSII houses, where their technology could be closely linked with those vendors’ implementation flows.
Since then, TSMC and other foundries have worked with the EDA ecosystem to better share process data so the EDA flow has access to it. “The biggest change in DFM in recent years has been that we’ve found ways to package process data and have it available to the DFM tools,” says Tom Quan, TSMC’s deputy director of design services marketing. “Then the EDA tools can tell the designer about lithography hot spots that need attention, and the latest generation of tools can also automatically fix these hot spots.”
The mechanism by which TSMC now shares process data is called DFM data kits (DDKs). TSMC monitors its lithography processes over time and gathers relevant manufacturing data that impacts yield. The way the data is packaged protects TSMC’s “secret sauce,” but exposes it to the EDA vendors’ flows. “We work with the EDA ecosystem partners to ensure their tool reads this data properly and uses it to analyze a given design in context of the process,” says Quan.
For the 90- and 65-nm nodes, TSMC’s DDKs encapsulate manufacturing data relevant to lithography, chemical-mechanical polishing (CMP), and critical-area analysis (CAA) of random and systematic defects caused by the process itself.
As of last year, however, TSMC began looking forward to the nodes beyond 65 nm. “The DDKs contain all the necessary information about hot spots that the EDA tools need to detect them. But for each tool vendor, we need to ensure that the way their tools detect hot spots is the same way we see it in manufacturing,” says Quan. The result was a new Unified DFM (UDFM) architecture announced last year.
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