FPGA usage divides into two primary segments. Historically, the foremost role of FPGAs has been to verify an ASIC, system-on-achip (SoC), or application-specific standard part (ASSP). Designers now will use FPGAs to prototype a portion or all of their design, to tweak the same, or as a platform to get ahead on developing system software. According to some industry experts, as many as 90% to 100% of ASICs today are prototyped on FPGAs.
For many years, a main application for FPGAs has involved the in-house construction of ASIC prototyping boards, some using a single FPGA and some with multiple chips. Anecdotes mention boards with as many as 50 FPGAs. Of course, the use of multiple devices requires designers to partition the design among them and handle associated timing issues. Now that a broad array of commercially built FPGA prototyping boards and verification systems is on the market, the build-versus-buy decision has become more complicated.
Others have turned to FPGAs as a production vehicle for their end products. Today’s FPGA, a far more capable animal than those of just a few years ago, embeds resources that lend themselves to a broad array of applications. Not so long ago, production use of FPGAs was limited to glue logic or relatively small applications. This is no longer the case.
FPGA vendors tend to be early adopters of cutting-edge process technologies, with vendors like Altera and Xilinx pushing these processes even into their Spartan and Cyclone low-cost device families. Designers thus find them attractive for mediumvolume consumer applications. Still, whatever you’re using FPGAs for, a tool chain must be in place to execute your design, verify its functionality, and place and route the design on the device itself.
ESL AND FPGAS DO MIX
Electronic system-level (ESL) tools are getting more attention from designers facing the faster-than-ever design and verification of complex designs. One ESL synthesis tool that can work in an FPGA flow is Forte Design Systems’ Cynthesizer. Despite being developed to meet the needs of ASIC/SoC designers targeting particular process technologies, Cynthesizer addresses a number of use models that include FPGAs, according to Mike Meredith, Forte’s vice president of technical marketing.
For instance, there’s high-speed functional validation of RTL code. “When an FPGA implementation is used for functional validation of RTL code, the FPGA is being used as a high-speed simulator,” says Meredith.
In such an instance, the goal is to verify the correctness of the RTL code before committing to silicon. Designers can synthesize a SystemC design using the .lib file and clock speed that will ultimately be used for the high-volume silicon implementation. Then, using Cynthesizer’s integration with Synopsys’ Synplify Pro, the RTL code can be targeted to a specific FPGA.
Because the FPGA is unlikely to achieve the aggressive timing of the ASIC implementation, the resulting FPGA will have to be run at a lower clock speed. However, functional verification can still proceed many times faster than using a software simulator, says Meredith.
High-level synthesis (HLS) tools also can target different process technologies and clock speed targets without changing the high-level source. Designers using an FPGA as a stepping stone to an ASIC implementation can exploit this capability to develop an FPGA prototype that runs as fast as possible. Subsequently, they will be able to automatically create ASIC RTL code optimized for the timing characteristics of their chosen process and foundry.
In addition to using FPGAs as a stepping stone toward an ASIC implementation, Forte is seeing more users turning to the FPGA as the ultimate production target. “These designers require RTL code targeted for the specific FPGA that they plan to use, so they use our FPGA-specific high-level synthesis flow,” says Meredith. Cynthesizer provides a fully automated integration with the Xilinx and Altera place-and-route tools, making it easy to go from SystemC source to a running FPGA.
BUIDLING AN ASIC-LIKE-FLOW
For most designers considering FPGAs as a verification vehicle, a cultural divide must be crossed. Writing well-crafted RTL code is the same no matter where it ends up being implemented, so design and coding styles change little. What does change, though, are the designers’ expectations.
“FPGA tools must get to a certain maturity level,” says Daniel Platzker, product line director for FPGA synthesis at Mentor Graphics (Fig. 1). “The ASIC flow is mature and designers are used to having everything required to eliminate respins, which are devastating. So the FPGA flow had to mature in similar fashion with much more simulation and verification.”
FPGA flows are maturing in the area of physical synthesis, which endows the synthesis flow with a built-in knowledge of the target FPGA’s architecture. Physical synthesis, a synthesis run that also completes placement, gives designers a much better handle on timing closure. Interconnect delays are the dominant factor in the timing of critical paths, and these delays are altogether unpredictable until completing placement.
One example of a physical synthesis tool, the Synopsys Synplify Premier, employs a graph-based placement engine to first map the design to the FPGA with global placement and routing and then optimize with detailed placement and local routing. Final routing is left to the FPGA vendor’s router.
“The on-chip resources you choose are what makes a huge difference in timing,” says Angela Sutton, staff product marketing manager for FPGA implementation products in the Synopsys Synplicity Business Group. “For example, there are some DSP resources on the Virtex 5. If you choose a particular resource in one iteration and another in the next, that will have a huge effect on timing. Locking that down is key in consistent timing estimates.”
Other vendors take a slightly different tack with physical synthesis. For instance, Mentor Graphics prefers to term it “physicalaware synthesis,” says Daniel Platzker, product line director with the FPGA Division at Mentor Graphics.
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